app
Adom Fields
Public Made by Adomby adom
Adom Fields: where the current and the heat go on your board.
main
John Lauer
0.9.4: package the 0.9.3 binary
edceb00
adom-fields 0.9.3 and 0.9.4
- Fix and verify (
adom-fields verify).- What it does: carries out fix-plan steps on a copy of the board file, solves the copy, and reports what the fix did. That is: the issues cleared and new, every solved number that moved and in which direction, and (with
--refill) the DRC errors the fix introduced. - What it applies: the copper edits the plan spells out. That means through vias (
add-vias) placed only on the net's own copper on two layers with 0.2 mm to other nets, and wider segments (widen) grown only as far as clearance allows. Each edit sees the earlier ones. - What it refuses: part, move, reroute and pour changes, with the reason, for the AI's layout pass or a person.
--refill: KiCad refills the zones and runs DRC on both boards first (service-kicad, else KiCad on the desktop through Adom Bridge). Neighbouring pours make room for the fix, and the two solves differ only by it.- On the 4-layer ESC:
- Thermal vias: four under each of two FETs clear both thermal-via issues and drop Q2 from +90.8 to +86.0 °C, with no new DRC errors.
- Widening: widening the four worst necks' traces (1.0 mm to between 1.1 and 2.0 mm, as clearance allows) lowers the Joule loss and every hot part by about 0.5 °C.
- What the report also shows: +VBAT's peak cell moves to the corner where a 2 mm segment meets one that could only reach 1.1 mm, and the neck issues remain. The traces are boxed in, and the real fix there is a layout change.
- An earlier pass caught its own mistake: it widened two neighbouring nets (+VBAT and the C-phase output) against the original geometry. KiCad's DRC reported four new clearance errors, and the edits now see each other.
- What it does: carries out fix-plan steps on a copy of the board file, solves the copy, and reports what the fix did. That is: the issues cleared and new, every solved number that moved and in which direction, and (with
0.9.4 is 0.9.3 as installed by pkg install (the same features).
# adom-fields 0.9.3 and 0.9.4
- **Fix and verify (`adom-fields verify`).**
- **What it does:** carries out fix-plan steps on a copy of the board file, solves the copy, and reports what the fix did. That is: the issues cleared and new, every solved number that moved and in which direction, and (with `--refill`) the DRC errors the fix introduced.
- **What it applies:** the copper edits the plan spells out. That means through vias (`add-vias`) placed only on the net's own copper on two layers with 0.2 mm to other nets, and wider segments (`widen`) grown only as far as clearance allows. Each edit sees the earlier ones.
- **What it refuses:** part, move, reroute and pour changes, with the reason, for the AI's layout pass or a person.
- **`--refill`:** KiCad refills the zones and runs DRC on both boards first (service-kicad, else KiCad on the desktop through Adom Bridge). Neighbouring pours make room for the fix, and the two solves differ only by it.
- **On the 4-layer ESC:**
- **Thermal vias:** four under each of two FETs clear both thermal-via issues and drop Q2 from +90.8 to +86.0 °C, with no new DRC errors.
- **Widening:** widening the four worst necks' traces (1.0 mm to between 1.1 and 2.0 mm, as clearance allows) lowers the Joule loss and every hot part by about 0.5 °C.
- **What the report also shows:** +VBAT's peak cell moves to the corner where a 2 mm segment meets one that could only reach 1.1 mm, and the neck issues remain. The traces are boxed in, and the real fix there is a layout change.
- **An earlier pass caught its own mistake:** it widened two neighbouring nets (+VBAT and the C-phase output) against the original geometry. KiCad's DRC reported four new clearance errors, and the edits now see each other.
0.9.4 is 0.9.3 as installed by `pkg install` (the same features).