AI Flow

{
  "board": "ESC G431 (Adom molecule: STM32G431, DRV8300, six BSC016N06NS, TPSM365 buck, INA181 current sense), 64 x 74 mm, 4 layers",
  "fab": "3rd party fab (copper ablation: keep as much copper as the electrical rules allow)",
  "copperUm": 35,
  "clearance": 0.2,
  "edgeClearance": 0.5,
  "inheritedErrors": 13,
  "inheritedErrorsNote": "six malformed MOSFET courtyards and seven U2 pad clearances come from the source libraries; they are counted separately and never fixed by the flow",
  "fixedRefs": [
    "MP1",
    "MP2",
    "MP3",
    "MP4",
    "MC1",
    "MC2",
    "MC3",
    "MC4",
    "MC5",
    "MC6",
    "MC7",
    "MC8",
    "MC9",
    "MC10",
    "MC11",
    "MC12",
    "MC13",
    "MC14",
    "MC15",
    "MC16",
    "MC17",
    "MC18",
    "MC19",
    "MC20",
    "MC21",
    "MC22",
    "MC23"
  ],
  "planes": {
    "GND": "In1.Cu",
    "+3V3": "In2.Cu"
  },
  "wideNets": {
    "+VBAT": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHA": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHB": [
      1.0,
      0.5,
      0.25
    ],
    "/DRV_SHC": [
      1.0,
      0.5,
      0.25
    ],
    "GND_OUT": [
      1.0,
      0.5,
      0.25
    ]
  },
  "midNets": {
    "+5V": [
      0.5,
      0.25
    ],
    "+12V": [
      0.5,
      0.25
    ]
  },
  "kelvin": {
    "U6.3": "R32.2",
    "U6.4": "R32.1"
  },
  "kelvinNote": "INA181 IN- (pad 3) taps the shunt's GND pad, IN+ (pad 4) taps its GND_OUT pad; dedicated traces, no plane stub, pour keepouts along them",
  "loads": {
    "+VBAT": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHA": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHB": {
      "amps": 20,
      "maxRiseC": 10
    },
    "/DRV_SHC": {
      "amps": 20,
      "maxRiseC": 10
    },
    "GND_OUT": {
      "amps": 20,
      "maxRiseC": 10
    },
    "+12V": {
      "amps": 0.5
    },
    "+5V": {
      "amps": 0.5
    }
  },
  "hot": {
    "Q1": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q3": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q5": {
      "watts": 0.6,
      "tabNet": "+VBAT"
    },
    "Q2": {
      "watts": 0.6,
      "tabNet": "/DRV_SHA"
    },
    "Q4": {
      "watts": 0.6,
      "tabNet": "/DRV_SHB"
    },
    "Q6": {
      "watts": 0.6,
      "tabNet": "/DRV_SHC"
    },
    "U1": {
      "watts": 0.5,
      "tabNet": "+VBAT",
      "note": "SOT-89 pad 2 (the tab) is +VBAT, the input; the +VBAT F.Cu block has a tongue down to it"
    }
  },
  "pours": [
    {
      "net": "GND",
      "layers": [
        "In1.Cu"
      ],
      "outline": true,
      "priority": 0,
      "connection": "solid",
      "name": "GND inner reference plane"
    },
    {
      "net": "+3V3",
      "layers": [
        "In2.Cu"
      ],
      "outline": true,
      "priority": 0,
      "connection": "solid",
      "name": "+3V3 inner reference plane"
    },
    {
      "net": "GND",
      "outline": true,
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "priority": 0,
      "connection": "thermal",
      "thermalGap": 0.3,
      "thermalBridge": 0.35,
      "name": "GND outer copper retention"
    },
    {
      "net": "+VBAT",
      "polygon": [
        [
          133.8,
          59.5
        ],
        [
          156,
          59.5
        ],
        [
          156,
          125.5
        ],
        [
          133.8,
          125.5
        ]
      ],
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "name": "Battery rail and high-side thermal column",
      "priority": 2,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHC",
      "polygon": [
        [
          156.2,
          75.5
        ],
        [
          167,
          75.5
        ],
        [
          167,
          89.7
        ],
        [
          150,
          89.7
        ],
        [
          150,
          82.4
        ],
        [
          156.2,
          82.4
        ]
      ],
      "layers": [
        "F.Cu"
      ],
      "name": "Phase C front load corridor",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHC",
      "polygon": [
        [
          149,
          82.5
        ],
        [
          167,
          82.5
        ],
        [
          167,
          89.7
        ],
        [
          130,
          89.7
        ],
        [
          130,
          86
        ],
        [
          149,
          86
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "name": "Phase C low-side thermal spreader",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHB",
      "polygon": [
        [
          156.2,
          90
        ],
        [
          167,
          90
        ],
        [
          167,
          103.7
        ],
        [
          150,
          103.7
        ],
        [
          150,
          96.4
        ],
        [
          156.2,
          96.4
        ]
      ],
      "layers": [
        "F.Cu"
      ],
      "name": "Phase B front load corridor",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHB",
      "polygon": [
        [
          149,
          96.5
        ],
        [
          158,
          96.5
        ],
        [
          158,
          90
        ],
        [
          167,
          90
        ],
        [
          167,
          109.5
        ],
        [
          158,
          109.5
        ],
        [
          158,
          103.7
        ],
        [
          149,
          103.7
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "name": "Phase B low-side thermal spreader",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHA",
      "polygon": [
        [
          156.2,
          104
        ],
        [
          167,
          104
        ],
        [
          167,
          121.5
        ],
        [
          150,
          121.5
        ],
        [
          150,
          110.4
        ],
        [
          156.2,
          110.4
        ]
      ],
      "layers": [
        "F.Cu"
      ],
      "name": "Phase A front load corridor",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "/DRV_SHA",
      "polygon": [
        [
          149,
          110.5
        ],
        [
          167,
          110.5
        ],
        [
          167,
          124.5
        ],
        [
          130,
          124.5
        ],
        [
          130,
          118
        ],
        [
          149,
          118
        ]
      ],
      "layers": [
        "B.Cu"
      ],
      "name": "Phase A low-side thermal spreader",
      "priority": 3,
      "connection": "solid"
    },
    {
      "net": "GND_OUT",
      "polygon": [
        [
          125,
          59.5
        ],
        [
          135.7,
          59.5
        ],
        [
          135.7,
          75
        ],
        [
          125,
          75
        ]
      ],
      "layers": [
        "F.Cu",
        "B.Cu"
      ],
      "name": "Shunt return to fixed battery contact",
      "priority": 3,
      "connection": "solid"
    }
  ],
  "solidAt": [
    "C45.2",
    "C43.2",
    "JP1.1",
    "MC18.1",
    "C36.2",
    "C9.2",
    "U1.1"
  ],
  "thermalVias": [
    {
      "pad": "Q1.5",
      "net": "+VBAT",
      "count": 4
    },
    {
      "pad": "Q3.5",
      "net": "+VBAT",
      "count": 4
    },
    {
      "pad": "Q5.5",
      "net": "+VBAT",
      "count": 4
    },
    {
      "pad": "Q2.5",
      "net": "/DRV_SHA",
      "count": 4
    },
    {
      "pad": "Q4.5",
      "net": "/DRV_SHB",
      "count": 4
    },
    {
      "pad": "Q6.5",
      "net": "/DRV_SHC",
      "count": 4
    }
  ],
  "stitchVias": [],
  "notPoured": [
    "/DRV_BSTA",
    "/DRV_BSTB",
    "/DRV_BSTC",
    "/SW",
    "/HSE_IN",
    "/HSE_OUT",
    "/COMP1_INM_IO1_BEMF_B",
    "/COMP1_INM_IO2_BEMF_C",
    "/COMP2_INM_IO1_BEMF_A",
    "/VBAT_SENSE",
    "/IBAT_SENSE",
    "+3V3",
    "/VDDA"
  ],
  "notPouredNote": "switching and bootstrap nodes, the crystal, the BEMF dividers and comparator inputs, the sense taps; +3V3 and /VDDA have the In2.Cu plane",
  "stitchViasNote": "inside both +VBAT rail blocks (F.Cu and B.Cu) and clear of other copper; a stitching via outside the pour is an unconnected item",
  "poursNote": "Fresh Astra placement: high-side tabs at x152.95 and y79/93/107; low-side tabs at x155.05 and y87/101/115. Front phase corridors connect the fixed phase contacts, and rear regions spread tab heat. Broad battery copper occupies the central power column. These polygons replace all geometry from the earlier placement; native refill, DRC and measured analyses determine acceptance.",
  "hotNote": "BSC016N06NS at 20 A phase current: I2R at 3 mOhm hot (Rds(on) 1.6 mOhm typ at 25 C) over one third of the electrical cycle (six-step) is 0.4 W, plus about 0.2 W of switching at 24 kHz: 0.6 W per FET. U1 is a linear regulator on the +VBAT tab: 0.5 W.",
  "hotMaxRiseC": 60,
  "hotMaxRiseNote": "the tab may sit 60 C above ambient at the stated dissipation (theta from the 40 C/W per square inch outer-copper heuristic of 0.1)",
  "thermalRevisionNote": "Q4 left arm was starved by routing and added only 0.67 mm2 of filled copper. Replaced by a connected rear extension at x158..167, y90..109.5 beside MC9. All electrical and thermal limits unchanged."
}