AI Flow

@@ -14,7 +14,7 @@ members = [ ]  [workspace.package]-version = "0.1.35"+version = "0.1.36" edition = "2021" license = "MIT" repository = "https://wiki.adom.inc/adom/adom-aiflow"

@@ -127,13 +127,13 @@ Everything below is what John has asked for, in the order it is likely to land. **Steps after the board (the flow grows at the back)** - **moleculize**: add the machine pins so the board can live in the probing workcell as a molecule. - **paste**: solder paste jetting calculations and analysis.-- **probe**: work out how to probe the board when it comes off the in-house fab's process.+- **probe**: work out how to probe the board when it comes off the 3rd party fab process.  **Analyses (0.2)** - **current 0.2**: cross-sections through the filled copper instead of the narrowest-track heuristic; a current-density heat map per net. - **thermal 0.2**: copper area weighted by distance from the tab, via conduction, the other layer's contribution; a heat map per hot part. - **impedance**: controlled-impedance and return-path checks on the nets the spec marks.-- **ablation**: the copper-kept metric per layer as a mill-time estimate for the in-house fab's process, so "least copper to ablate" is a number the AI can push.+- **ablation**: the copper-kept metric per layer as a mill-time estimate for the 3rd party fab process, so "least copper to ablate" is a number the AI can push.  **The video (0.2)** - The step's own code frames the shot: zoom to fit before a landing, the part on screen when a move lands.

@@ -64,7 +64,7 @@ AI Flow's binary is the instrument, the gates and the hands; the judgement for e | step | skill | |---|---| | a brief or a video to reproduce, before any board exists | `aiflow-intake` |-| choosing parts, the fab profile (in-house by default, JLCPCB on request), symbols, footprints and 3D models | `aiflow-sourcing` |+| choosing parts, the fab profile (3rd party fab by default, JLCPCB on request), symbols, footprints and 3D models | `aiflow-sourcing` | | datasheet equations, stocked values, margins | `aiflow-circuit-design` | | loop and transient simulation, vendor PSpice models | `aiflow-simulate` | | schematic and board from a netlist, KiCad 10 traps | `aiflow-schematic-to-board` |

⋯ 1 unchanged line ⋯

@@ -5,7 +5,7 @@ Ten new skills from the second board built with AI Flow (a 12 V to 5 V, 1 A buck | skill | what it guides | |---|---| | `aiflow-intake` | a brief (or a video to reproduce) to requirements, with the clock started at the prompt |-| `aiflow-sourcing` | parts and CAD: the in-house fab profile by default (Mouser plus Adom stocked parts), JLCPCB on request; manufacturer CAD first, then distributor CAD, then the wiki, then your own labelled model |+| `aiflow-sourcing` | parts and CAD: the 3rd party fab profile by default (Mouser plus Adom stocked parts), JLCPCB on request; manufacturer CAD first, then distributor CAD, then the wiki, then your own labelled model | | `aiflow-circuit-design` | datasheet equations in a script, stocked-value searches, margins and the part-reading checklist | | `aiflow-simulate` | ngspice loop and switching models, vendor PSpice models, and a written design conclusion | | `aiflow-schematic-to-board` | schematic and board generated from one netlist, and the KiCad 10 traps |

@@ -0,0 +1,3 @@+# AI Flow 0.1.36++Documentation only: the fab named in the silkscreen guidance, the flow steps, the example spec and the recorded run logs is now written as "3rd party fab", with its process details (text sizes, laser process, copper ablation) kept. The sourcing and rules profile `inhouse` is now `fab`. The binary is unchanged apart from the version.

@@ -50,7 +50,7 @@ One row per human prompt: the AI's time on it, the idle it did not get charged f | 32 | 2026-09-16T22:20:32Z | (open) | 0.0 | 0 | follow-up (no prompt mark; say `prompt --text` next time) | | 33 | 2026-09-16T22:36:36Z | (open) | 0.0 | 0 | follow-up (no prompt mark; say `prompt --text` next time) | | 34 | 2026-09-16T22:36:36Z | (open) | 26.8 | 26 | Finish component hero bindings, page quality and model qualification; resolve J1; refresh  |-| 35 | 2026-09-16T23:29:47Z | (open) | 49.9 | 0 | Add a rich two-sided silkscreen stage and reusable InstaPCB silkscreen guidance; apply it  |+| 35 | 2026-09-16T23:29:47Z | (open) | 49.9 | 0 | Add a rich two-sided silkscreen stage and reusable 3rd party fab silkscreen guidance; apply it  | | 36 | 2026-09-17T00:19:39Z | 2026-09-17T00:20:42Z | 1.1 | 0 | Record silkscreen population and actual rework as individual labels or useful groups | | 37 | 2026-09-17T00:20:42Z | (open) | 2.2 | 0 | follow-up (no prompt mark; say `prompt --text` next time) | | 38 | 2026-09-17T00:22:52Z | 2026-09-17T00:40:52Z | 18.0 | 0 | Use curved leaders, smaller contact function text, and positionally adjacent contact label |@@ -1055,17 +1055,17 @@ Percent of each plan limit used, as the provider reports it, at the start of the - pr https://wiki.adom.inc/adom/adom-aiflow/prs/11: Correct URL: rebuilt and tested hero-binding, scoped permission and native visibility guidance - issue https://wiki.adom.inc/adom/adom-aiflow/issues/23: Expose active external-work spans instead of misclassifying long AI work as idle - pr https://wiki.adom.inc/adom/adom-aiflow/prs/12: Two-sided service silkscreen stage; rebuilt and tested-- pr https://wiki.adom.inc/adom/instapcb/prs/1: Reusable InstaPCB silkscreen skill in existing repo+- pr #1 on the 3rd party fab's page: Reusable 3rd party fab silkscreen skill in existing repo - issue https://wiki.adom.inc/adom/kicad-bridge/issues/102: Native viewer must bind evidence to exact PCB editor; missing silk primitives belong in bridge - issue https://wiki.adom.inc/adom/wiki/issues/210: Nested README media resolution failure and verified absolute-URL workaround - pr https://wiki.adom.inc/adom/adom-aiflow/prs/13: Consolidated silk guidance: both faces, all test points, closer references, 0.3/0.2mm values-- pr https://wiki.adom.inc/adom/instapcb/prs/2: Consolidated silk guidance: both faces, all test points, closer references, 0.3/0.2mm values+- pr #2 on the 3rd party fab's page: Consolidated silk guidance: both faces, all test points, closer references, 0.3/0.2mm values - pr https://wiki.adom.inc/adom/adom-aiflow/prs/14: Progressive silkscreen recording and real rework; release build and CLI plan verified-- pr https://wiki.adom.inc/adom/instapcb/prs/3: Reusable skill teaches progressive label capture and honest replay provenance+- pr #3 on the 3rd party fab's page: Reusable skill teaches progressive label capture and honest replay provenance - pr https://wiki.adom.inc/adom/adom-aiflow/prs/15: Both-face positional labels, curved leaders and exhaustive local values; rebuilt CLI hints tested-- pr https://wiki.adom.inc/adom/instapcb/prs/4: Skill corrects remote-table fallback and requires paired microtext and positional contact labels+- pr #4 on the 3rd party fab's page: Skill corrects remote-table fallback and requires paired microtext and positional contact labels - pr https://wiki.adom.inc/adom/adom-aiflow/prs/16: Always refresh and verify both native views after edits; root skill and emitted hints rebuilt/tested-- pr https://wiki.adom.inc/adom/instapcb/prs/5: Skill requires current 2D and 3D views, preserving work and avoiding stale windows+- pr #5 on the 3rd party fab's page: Skill requires current 2D and 3D views, preserving work and avoiding stale windows - pr https://wiki.adom.inc/adom/eda-engineering/prs/1: Shared component hero and LED appearance skills with source-preserving generator - pr https://wiki.adom.inc/adom/eda-engineering/prs/2: Include hero and LED skills and shared generator in installed package - issue https://wiki.adom.inc/adom/kicad-bridge/issues/103: Correct misleading native-parser availability report@@ -1073,12 +1073,12 @@ Percent of each plan limit used, as the provider reports it, at the start of the - issue https://wiki.adom.inc/adom/kicad-bridge/issues/105: Native 3D framing belongs in the bridge - pr https://wiki.adom.inc/adom/adom-aiflow/prs/17: Shared live silkscreen dashboard, solver events and whole-board obstacle audit; built and tested - pr https://wiki.adom.inc/adom/adom-aiflow/prs/18: CLI-driven replay recording and automatic run artifact retention-- pr https://wiki.adom.inc/adom/instapcb/prs/6: Complete fitted-body and via obstacle coverage with locality-first silkscreen placement+- pr #6 on the 3rd party fab's page: Complete fitted-body and via obstacle coverage with locality-first silkscreen placement - pr https://wiki.adom.inc/adom/adom-aiflow/prs/20: Fresh grouped typography, contact border consistency, pad-facing alignment and native preflight; tested development draft-- pr https://wiki.adom.inc/adom/instapcb/prs/7: Silkscreen design guidance: semantic blocks, pad-facing text, common contact frames and ESC phase prominence+- pr #7 on the 3rd party fab's page: Silkscreen design guidance: semantic blocks, pad-facing text, common contact frames and ESC phase prominence - pr https://wiki.adom.inc/adom/adom-aiflow/prs/21: Rejected and retook camera-lagged replay; record active group bounds independently - pr https://wiki.adom.inc/adom/adom-aiflow/prs/22: Native Rust interior documentation solver and full priority checklist-- pr https://wiki.adom.inc/adom/instapcb/prs/8: Interior documentation and human-readable silkscreen review priorities+- pr #8 on the 3rd party fab's page: Interior documentation and human-readable silkscreen review priorities - pr https://wiki.adom.inc/adom/adom-aiflow/prs/23: Recording now honors follow-off and supports full-board face population - issue https://wiki.adom.inc/adom/adom-aiflow/issues/27: Hidden webview throttles canvas capture; visible-tab retakes verified 

@@ -36,11 +36,11 @@ flow "board": Starts with component identity, reusable CAD review and native lib   step fields     both    the fields on the board: adom-fields solves the current density of every loaded net, the heat flow in each copper layer with the vias, and the temperature over the board; the AI reads the issues and walks the board in the app on camera   step nets       binary  walk the key nets on camera: each loaded, wide or Kelvin net selected as a whole so the editor highlights its pours, tracks, vias and pads together, framed with Zoom to Selection   step silkscreen ai      Make both faces useful in real service: references and values, verified connector and machine-contact pinouts, polarity, board identity and bring-up labels; review native plots and assembled visibility.-    1. Read the InstaPCB silkscreen skill for the selected process; reserve label space during placement and finalize after copper and analysis stabilize. Use both faces, a clear font-size hierarchy, and the approved process profile for small secondary text.+    1. Read the 3rd party fab silkscreen skill for the selected process; reserve label space during placement and finalize after copper and analysis stabilize. Use both faces, a clear font-size hierarchy, and the approved process profile for small secondary text.     2. Build a source-backed label manifest from actual schematic, pad numbers, nets and approved requirements. Include reference/value pairs, connector pinouts, power polarity, test points, switch/LED functions, revision and documentation link. Never infer voltage/current ratings from net names or component absolute maxima.     3. For every machine pin, machine contact and edge-pin connector, repeat its reference/pin number and verified signal or power function on BOTH faces. A mounted board may expose only one side during debugging. Put the repeated labels beside the same physical connection where possible; when crowded, use an unambiguous nearby keyed legend on that face. A pinout table on the other face alone does not satisfy this check. Review both faces in the mounted-access context, with bottom text correctly mirrored and pin numbering preserved.     4. Every test point MUST have visible silkscreen identifying both its reference and verified net/signal or measurement function. Prioritize these labels before ordinary component values. Keep them adjacent to the accessible probe pad, or use a short unambiguous leader/key on the same accessible face when crowded. Check complete test-point coverage against the actual board; missing or ambiguous labels are unresolved findings, never silently omitted. Repeat on the opposite face when useful for mounted-board debugging, without implying a probe pad exists there.-    5. Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense InstaPCB artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.+    5. Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense 3rd party fab artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.     6. Avoid mask openings, contact surfaces, holes, fiducials and bodies that hide labels. Inspect bottom mirroring, actual-size legibility and both native 2D/3D faces. Use EDA bridge text/plot/DRC operations; give missing primitives back to the bridge.     7. Run native DRC against the chosen fab profile and compare with the baseline. Preserve connectivity, placement, copper, outline and model transforms for silk-only edits. Register the label manifest and top/bottom evidence; return here when placements or pinouts change.   step 3d         binary  the 3D walkthrough: the viewer opened from the editor, then fit, top, tilt, orbit, zoom in, swing, front, bottom, flip, top, fit, all by menu command, no mouse

@@ -1,6 +1,6 @@ {   "board": "ESC G431 (Adom molecule: STM32G431, DRV8300, six BSC016N06NS, TPSM365 buck, INA181 current sense), 64 x 74 mm, 4 layers",-  "fab": "InstaPCB (copper ablation: keep as much copper as the electrical rules allow)",+  "fab": "3rd party fab (copper ablation: keep as much copper as the electrical rules allow)",   "copperUm": 35,   "clearance": 0.2,   "edgeClearance": 0.5,

@@ -9,7 +9,7 @@ The order below is explicit: a lower priority cannot buy a collision, incorrect 3. **Board-purpose importance.** Before placement, classify the board and rank its human interfaces. On ESCs, prominently label PHASE A/B/C and battery polarity/ground. Other boards get their own appropriate prominent interfaces, supply limits and critical warnings. Functional terminal names may outrank MC/J references. Use only sourced descriptions/limits. 4. **Locality and association.** Keep each name/value pair atomic and close to its component. For edge contacts prefer the space between contact and board edge, consistently across a row; use inside placement only when needed. Pin labels face their target: right-aligned left of the pad, left-aligned right of it, reversed appropriately for a readable bottom-face view. Use curved pointers when association is unclear. 5. **Group design.** Repeated contact frames default on, with a user-off option. Solve common left/right rails, width/height, padding and rhythm for a row/column. Do not stretch a frame after checking collisions. Clearance gaps and exceptional font/inside placements are explicit. Calculation bounds are dashed and translucent; only actual manufacturing text/pointers/frames are opaque solid strokes.-6. **Readable typography.** Maximize font size within the above constraints. Start ordinary references around 0.8 mm and values around 0.4 mm, with values smaller than references. Important interfaces often justify 1.0–1.4 mm or more where space permits. The user-authorized in-house fab 0.3/0.2 mm value text is a last resort, not a default or a general fabrication guarantee. Document the selected sizes and any tiny-text compromise.+6. **Readable typography.** Maximize font size within the above constraints. Start ordinary references around 0.8 mm and values around 0.4 mm, with values smaller than references. Important interfaces often justify 1.0–1.4 mm or more where space permits. The user-authorized 3rd party fab 0.3/0.2 mm value text is a last resort, not a default or a general fabrication guarantee. Document the selected sizes and any tiny-text compromise. 7. **Interior documentation pass.** Reserve readable open INTERIOR regions for a source-backed board description, identity/revision, service instructions and reference tables. Prefer an interior layout at a readable font over a slightly larger edge layout. Keep physical terminal labels local. Preserve semantic blocks, left-aligned visible text, heading hierarchy and ordered rows. Reflow or split a large table into coherent columns before pushing it to the rim. Slight, quantized row-spacing increases may avoid vias; do not move lines independently or reorder them. If the middle cannot fit safely, report the blocking geometry, attempted sizes and explicit edge fallback. Include what the board does, not just a project code. 8. **Independent verification and final visual pass.** Check every text and stroke ahead of the EDA, then native DRC and native text/geometry read-back. Inspect top and bottom in both the editor and its refreshed 3D viewer. Review left alignment, common rails, name/value hierarchy, pin-1/polarity, no text hidden by bodies, no holes under text, and whether documentation uses interior space sensibly. Repair the general rule when a native check reveals a defect. 9. **Evidence.** Replay all required groups and real rework with active text sizes. Isolate faces and show the bottom from below (or explicitly mirrored from above). Record 1920×1080; frame the complete active group independently of manual inspection camera movement. Include final native EDA proof. Inspect contact sheets and actual webview playback. Never describe the replay as recorded internal AI reasoning or omit unresolved decisions from the report.

@@ -1,13 +1,13 @@ # Two-sided service silkscreen -The `silkscreen` AI-owned stage runs after analysis/net review and before the final native 3D tour. Plan label space at placement time. Read the in-house fab's silkscreen skill (internal) when building for it.+The `silkscreen` AI-owned stage runs after analysis/net review and before the final native 3D tour. Plan label space at placement time. Read the reusable 3rd party fab's silkscreen skill (internal).   Treat silkscreen as the board's built-in service manual. Add useful information generously, with a visual hierarchy and space between labels. Do not fill space with ambiguous or unreadable text.  ## Process profile and provenance -For the in-house fab profile requested by Adam (Adom CEO, 2026-09-16), use approximately 0.8 mm reference designators and 0.5 mm secondary value text where space allows. He reports that the in-house fab's process can render readable 0.5 mm text. This is a named process target, not a universal fab minimum or a measured acceptance result. Verify the current station profile for stroke width, contrast, mask registration and clearances; retain the profile/version and inspect a physical coupon when fabrication qualification is required. Do not infer minimum stroke from text height. Preserve other fabs' rules and never disable DRC globally to force microtext through. Treat two-sided marking cost as a property of the selected service, not a universal free option.+For the 3rd party fab profile requested by Adam (Adom CEO, 2026-09-16), use approximately 0.8 mm reference designators and 0.5 mm secondary value text where space allows. He reports that the 3rd party fab's UV fiber laser process can render readable 0.5 mm text. This is a named process target, not a universal fab minimum or a measured acceptance result. Verify the current station profile for stroke width, contrast, mask registration and clearances; retain the profile/version and inspect a physical coupon when fabrication qualification is required. Do not infer minimum stroke from text height. Preserve other fabs' rules and never disable DRC globally to force microtext through. Treat two-sided marking cost as a property of the selected service, not a universal free option.  ## Plan before placement; finish after copper stabilizes @@ -16,8 +16,8 @@ For the in-house fab profile requested by Adam (Adom CEO, 2026-09-16), use appro 3. Label power inputs and returns, polarity, connector pin 1 and every accessible signal, machine pin/contact functions, programming/debug pinout, switch actions, LED meanings, test points and mounting orientation. Verify pin labels against actual numbered pads and nets, not the connector's apparent geometry. A net name does not establish a safe voltage or current rating. Print voltage range, maximum current and other limits only with approved design evidence; distinguish input rating, rail nominal voltage and absolute maximum.    Every test point MUST have visible silkscreen identifying both its reference and verified net/signal or measurement function. Prioritize these labels before ordinary component values. Keep them adjacent to the accessible probe pad, or use a short unambiguous leader/key on the same accessible face when crowded. Check complete test-point coverage against the actual board; missing or ambiguous labels are unresolved findings, never silently omitted. Repeat on the opposite face when useful for mounted-board debugging, without implying a probe pad exists there. -4. Use approximately 1.2–2.0 mm for board identity and critical connection labels, 0.8 mm for references and 0.5 mm for values/secondary notes under the named in-house fab profile. These are starting sizes, not mandatory packing rules. Prefer horizontal text and consistent reading directions; rotate to follow a connector only when that aids use. Use familiar engineering notation (10k, 100nF, 4.7uF); distinguish value, tolerance and voltage rating. Give every resistor/capacitor its reference plus a nearby value; search microtext placements before declaring a space constraint. Long IC MPNs may belong in a back-side key rather than in congested assembly space.-Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense in-house fab artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.+4. Use approximately 1.2–2.0 mm for board identity and critical connection labels, 0.8 mm for references and 0.5 mm for values/secondary notes under the named 3rd party fab profile. These are starting sizes, not mandatory packing rules. Prefer horizontal text and consistent reading directions; rotate to follow a connector only when that aids use. Use familiar engineering notation (10k, 100nF, 4.7uF); distinguish value, tolerance and voltage rating. Give every resistor/capacitor its reference plus a nearby value; search microtext placements before declaring a space constraint. Long IC MPNs may belong in a back-side key rather than in congested assembly space.+Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense 3rd party fab artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.  5. For every machine pin, machine contact and edge-pin connector, repeat its reference/pin number and verified signal or power function on BOTH faces. A mounted board may expose only one side during debugging. Put the repeated labels beside the same physical connection where possible; when crowded, use a short clear leader to the actual connection on that face; a remote keyed legend is supplementary only. A pinout table on the other face alone does not satisfy this check. Review both faces in the mounted-access context, with bottom text correctly mirrored and pin numbering preserved. Use both F.SilkS and B.SilkS (or the EDA's native equivalents). Bottom text must read correctly when viewed from underneath, with the EDA's proper mirror setting; do not reverse the string. Put a clear pinout/service key on the less crowded face, mapped to reference and pad number. Copper/pour labels identify a verified net; avoid implying that hidden traces are visible or electrically isolated. 6. Protect exposed pads, solder-mask openings, test contacts, holes, board edges, fiducials, optical windows, component courtyards and mechanical interfaces. Consider visible space with components fitted: body footprints may obscure text even when DRC passes. Retain assembly-only markings on fabrication layers if useful, but do not count them as visible silkscreen. Never move copper or parts merely to force extra text without a recorded design return.@@ -52,7 +52,7 @@ Film real leader placement and ref/function resizing as part of progressive silk  ## Complete local value coverage -For the requested in-house fab profile, attempt a nearby value for EVERY resistor and capacitor, including rotated components and references. Search both orientations and adjacent sides at 0.5, 0.3 and 0.2 mm as needed, preserving an unmistakable reference/value association. Do not skip values merely because the reference is rotated, an initial placement fails, or a bottom table exists. Repack nearby silk or use a clear short leader when necessary. Audit actual-board value coverage and report each unresolved value explicitly; a back-side key is supplementary, not completion. Retain native mask/overlap checks and distinguish requested artwork sizes from measured physical legibility.+For the requested 3rd party fab profile, attempt a nearby value for EVERY resistor and capacitor, including rotated components and references. Search both orientations and adjacent sides at 0.5, 0.3 and 0.2 mm as needed, preserving an unmistakable reference/value association. Do not skip values merely because the reference is rotated, an initial placement fails, or a bottom table exists. Repack nearby silk or use a clear short leader when necessary. Audit actual-board value coverage and report each unresolved value explicitly; a back-side key is supplementary, not completion. Retain native mask/overlap checks and distinguish requested artwork sizes from measured physical legibility.  ## Keep both native views current after every update 

@@ -1,6 +1,6 @@ {   "board": "ESC G431 (Adom molecule: STM32G431, DRV8300, six BSC016N06NS, TPSM365 buck, INA181 current sense), 64 x 74 mm, 4 layers",-  "fab": "in-house fab (copper ablation: keep as much copper as the electrical rules allow)",+  "fab": "3rd party fab (copper ablation: keep as much copper as the electrical rules allow)",   "copperUm": 35,   "clearance": 0.2,   "edgeClearance": 0.5,

@@ -157,16 +157,16 @@       "who": "ai",       "does": "Make both faces useful in real service: references and values, verified connector and machine-contact pinouts, polarity, board identity and bring-up labels; review native plots and assembled visibility. Offer the optional shared silkscreen dashboard: real solver events, candidate reasons, live/replay separation, fitted-model inspection and separately recorded detailed/5s replays. Audit every fitted body and every via/hole across the whole board, both faces, with coverage counts. Missing Fab geometry is not free space; native DRC does not establish fitted visibility. Keep unresolved labels explicit and do not apply an incomplete layout. Native geometry/edit/undo/refresh belongs to the EDA bridge.",       "workflow": [-        "Read the in-house fab's silkscreen skill for the selected process; reserve label space during placement and finalize after copper and analysis stabilize. Use both faces, a clear font-size hierarchy, and the approved process profile for small secondary text.",+        "Read the 3rd party fab silkscreen skill for the selected process; reserve label space during placement and finalize after copper and analysis stabilize. Use both faces, a clear font-size hierarchy, and the approved process profile for small secondary text.",         "Build a source-backed label manifest from actual schematic, pad numbers, nets and approved requirements. Include reference/value pairs, connector pinouts, power polarity, test points, switch/LED functions, revision and documentation link. Never infer voltage/current ratings from net names or component absolute maxima.",         "For every machine pin, machine contact and edge-pin connector, repeat its reference/pin number and verified signal or power function on BOTH faces. A mounted board may expose only one side during debugging. Put the repeated labels beside the same physical connection where possible; when crowded, use a short clear leader to the actual connection on that face; a remote keyed legend is supplementary only. A pinout table on the other face alone does not satisfy this check. Review both faces in the mounted-access context, with bottom text correctly mirrored and pin numbering preserved.",         "Every test point MUST have visible silkscreen identifying both its reference and verified net/signal or measurement function. Prioritize these labels before ordinary component values. Keep them adjacent to the accessible probe pad, or use a short unambiguous leader/key on the same accessible face when crowded. Check complete test-point coverage against the actual board; missing or ambiguous labels are unresolved findings, never silently omitted. Repeat on the opposite face when useful for mounted-board debugging, without implying a probe pad exists there.",-        "Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense in-house fab artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.",+        "Keep each reference unmistakably associated with its own component. Prefer reducing reference font size locally over moving a label farther away. Aim for complete reference coverage; use a short clear leader only when proximity alone is ambiguous. Treat approximately 0.8 mm as an initial reference size, not a minimum. For dense 3rd party fab artwork Adam explicitly permits secondary values at 0.3 mm or even 0.2 mm (2026-09-16); try 0.5, 0.3 then 0.2 mm while preserving the ref/value pairing and required stroke/spacing. These tiny sizes are user-requested artwork options, not independently verified laser-process capability. Keep the actual sizes and any unresolved physical legibility/DFM limits in the review; do not silently omit labels or globally weaken fab rules. Inspect the result at actual size and close-up.",         "Avoid mask openings, contact surfaces, holes, fiducials and bodies that hide labels. Inspect bottom mirroring, actual-size legibility and both native 2D/3D faces. Use EDA bridge text/plot/DRC operations; give missing primitives back to the bridge.",         "Run native DRC against the chosen fab profile and compare with the baseline. Preserve connectivity, placement, copper, outline and model transforms for silk-only edits. Register the label manifest and top/bottom evidence; return here when placements or pinouts change.",         "Record BEFORE the first silkscreen mutation: show labels appearing individually or in small meaningful groups, pairing references with smaller values. Film actual moves, resizing, rotations and overlap corrections in order; preserve a timestamped operation/reason sidecar and raw uncaptioned footage. Use native bridge edits and refresh, never invented verbs. If native incremental editing is missing, file the bridge gap; identify any checkpoint reconstruction as a replay, never as original live placement. Keep a detailed action cut and use 3\u20135 seconds of accelerated population/rework in the final 120-second film. Read docs/silkscreen.md for recording and evidence rules.",         "Require positional contact labels on BOTH faces: a pinout table is supplementary, never a substitute for text beside each actual machine contact, machine pin or edge connection. Separate primary reference (MC10) and smaller secondary function (DSHOT) as independently sized paired text. Prefer consistent reading directions. Where association remains ambiguous, add a short gentle curved silkscreen leader ending outside the intended pad mask opening; avoid crossings and obstacles. Verify one-to-one pad association, bottom mirroring, label/leader clearance and legibility in close-up native views and DRC. Film real additions and rework; retain mapping and unresolved constraints. See docs/silkscreen.md.",-        "For the requested in-house fab profile, attempt a nearby value for EVERY resistor and capacitor, including rotated components and references. Search both orientations and adjacent sides at 0.5, 0.3 and 0.2 mm as needed, preserving an unmistakable reference/value association. Do not skip values merely because the reference is rotated, an initial placement fails, or a bottom table exists. Repack nearby silk or use a clear short leader when necessary. Audit actual-board value coverage and report each unresolved value explicitly; a back-side key is supplementary, not completion. Retain native mask/overlap checks and distinguish requested artwork sizes from measured physical legibility.",+        "For the requested 3rd party fab profile, attempt a nearby value for EVERY resistor and capacitor, including rotated components and references. Search both orientations and adjacent sides at 0.5, 0.3 and 0.2 mm as needed, preserving an unmistakable reference/value association. Do not skip values merely because the reference is rotated, an initial placement fails, or a bottom table exists. Repack nearby silk or use a clear short leader when necessary. Audit actual-board value coverage and report each unresolved value explicitly; a back-side key is supplementary, not completion. Retain native mask/overlap checks and distinguish requested artwork sizes from measured physical legibility.",         "After EVERY board or model update, refresh and verify BOTH the native 2D editor and its linked 3D viewer before showing/reporting completion. Check exact saved board revision and actual rendered changes in both windows. Reload cached models; if reopening is required preserve unsaved user work, close only task-owned stale windows and retain one current editor/viewer pair. Never overwrite a newer disk edit from a stale editor. Use native bridge controls and keep foreground preferences.",         "Search space before shrinking text: 0.2 mm is a last resort. Use native text bounds and per-face body/pad/mask/via/silk obstacles, keep separate boxes for ref/value pairs, repack neighboring labels, preserve pin-row order and validate leader paths. Run silkscreen-layout on candidates; bounded search is not native verification. Apply by stable item ID, compare native DRC with baseline, inspect fitted visibility, and refresh BOTH native views. See docs/silkscreen.md."       ],@@ -234,7 +234,7 @@     },     {       "name": "probe",-      "does": "how to probe the board when it comes off the in-house fab's process"+      "does": "how to probe the board when it comes off the 3rd party fab process"     }   ],   "clips": "every `step <name>` stops the previous step's clip and starts a new window recording tagged with the step, when the board is open on a test box; run.json captures[] carries one entry per clip with its step, start, stop and file, and deliver lists them; the final video is cut from these clips, one segment per step, so two engines' videos line up step for step; a return (step <name> --back --why) is a new visit and gets its own clip, tagged <step>-<visit> with the reason, so the rework is on camera and the final cut can show the loop",

@@ -1,7 +1,7 @@ {   "slug": "adom-aiflow",   "type": "app",-  "version": "0.1.35",+  "version": "0.1.36",   "title": "AI Flow",   "description": "Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board. One Rust binary with a crate per step (placement helpers, a grid router with Kelvin taps, pours with keepouts, KiCad's DRC gate, live landing through the KiCad Bridge, copper measurement, current and thermal analysis) and a finish line that refuses an unfinished board. Every command answers with hints for the AI; every turn, its thinking time and every rework loop go into run.jsonl, so Claude, Codex and any other engine are compared on the same flow. KiCad today; Altium, Fusion and Adom's own web apps next.",   "summary": "Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board. The AI thinks its way from placement through routing, pours, current and thermal analysis to a delivered video; the binary does the fast, deterministic parts of every step, hands back hints, and keeps a ledger of every turn, every return to an earlier step, and the clock from the prompt to done.",

@@ -1,7 +1,7 @@ {   "slug": "adom-aiflow",   "type": "app",-  "version": "0.1.35",+  "version": "0.1.36",   "title": "AI Flow",   "description": "Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board. One Rust binary with a crate per step (placement helpers, a grid router with Kelvin taps, pours with keepouts, KiCad's DRC gate, live landing through the KiCad Bridge, copper measurement, current and thermal analysis) and a finish line that refuses an unfinished board. Every command answers with hints for the AI; every turn, its thinking time and every rework loop go into run.jsonl, so Claude, Codex and any other engine are compared on the same flow. KiCad today; Altium, Fusion and Adom's own web apps next.",   "summary": "Adom's AI Flow: a tool to help the AI follow all of the steps it takes to build a board. The AI thinks its way from placement through routing, pours, current and thermal analysis to a delivered video; the binary does the fast, deterministic parts of every step, hands back hints, and keeps a ledger of every turn, every return to an earlier step, and the clock from the prompt to done.",

@@ -64,7 +64,7 @@ AI Flow's binary is the instrument, the gates and the hands; the judgement for e | step | skill | |---|---| | a brief or a video to reproduce, before any board exists | `aiflow-intake` |-| choosing parts, the fab profile (in-house by default, JLCPCB on request), symbols, footprints and 3D models | `aiflow-sourcing` |+| choosing parts, the fab profile (3rd party fab by default, JLCPCB on request), symbols, footprints and 3D models | `aiflow-sourcing` | | datasheet equations, stocked values, margins | `aiflow-circuit-design` | | loop and transient simulation, vendor PSpice models | `aiflow-simulate` | | schematic and board from a netlist, KiCad 10 traps | `aiflow-schematic-to-board` |

@@ -40,7 +40,7 @@ cd design && python3 calcs.py     # prints the table, writes calcs.json  ## 2. Search the stock, not the E-series -On the in-house profile the resistor set is 41 values (aiflow-sourcing). Enumerate singles and series pairs, keep the constraints the datasheet puts on the network (divider current, top resistor range for the feed-forward cap), and sort by error, then part count:+On the 3rd party fab profile the resistor set is 41 values (aiflow-sourcing). Enumerate singles and series pairs, keep the constraints the datasheet puts on the network (divider current, top resistor range for the feed-forward cap), and sort by error, then part count:  ```python for rtop_parts in singles + pairs:

@@ -60,7 +60,7 @@ Every question stops the clock's value for nothing. Decide what you can, state t | Decide yourself (state it) | Ask (once, all together) | |---|---| | Form factor: an Adom molecule for Adom work (aiflow-molecule) | A number the brief contradicts or leaves ambiguous and that changes the design (5 V or 3.3 V out?) |-| Fab target: our own in-house PCB fab by default | A mating connector, enclosure or mechanical constraint you cannot see |+| Fab target: the 3rd party fab by default | A mating connector, enclosure or mechanical constraint you cannot see | | Sourcing profile: follows the fab target (aiflow-sourcing) | Cost or quantity ceilings when they would change part choice | | Input range margin, derating, test points, a power-good LED | Anything that spends money or touches another person's work | | Deliverables the flow always makes (calcs, sim, schematic, board, 3D, video, clips page) | Deliverables beyond the flow (a scaffold layout for a specific workcell, a vendor-model run, a PR to someone's page) when the brief does not name them |@@ -79,8 +79,8 @@ One file beside the design. Minimum shape:   "outputs": [{"name": "VOUT", "V": 5.0, "tol_pct": 3, "I_A": 1.0}],   "interfaces": {"power": ["VIN", "GND", "VOUT"], "control": ["EN"], "monitor": ["VMON"], "probe": ["SW", "FB", "VOUT", "GND"]},   "formFactor": {"kind": "molecule", "pin": "MachinePinMediumShort", "grid_mm": 2},-  "fab": {"target": "inhouse", "layers": 2, "thickness_mm": 1.6, "design_copper_oz": 0.5},-  "sourcing": {"profile": "inhouse"},+  "fab": {"target": "fab", "layers": 2, "thickness_mm": 1.6, "design_copper_oz": 0.5},+  "sourcing": {"profile": "fab"},   "deliverables": ["calcs", "ngspice loop + transient", "vendor-model check", "schematic", "board", "3D models", "molecule publish", "scaffold + probe plan", "video", "clips page"],   "assumptions": [],   "preBoard": []@@ -88,7 +88,7 @@ One file beside the design. Minimum shape: ```  - **inputs / outputs**: every rail with nominal, range and current. A design range wider than the brief is fine; say why.-- **fab.target**: `inhouse` (default) or `jlcpcb`. It picks `sourcing.profile` and the DRC rules profile (aiflow-molecule).+- **fab.target**: `fab` (default) or `jlcpcb`. It picks `sourcing.profile` and the DRC rules profile (aiflow-molecule). - **deliverables**: everything the human asked for, including the steps after `finish` (molecule publish, scaffold placement, probe plan, vendor simulation). A deliverable not listed here gets forgotten.  ## 6. Hand off@@ -99,5 +99,5 @@ Read the file back to the human in five lines or fewer (rails, form factor, fab  - The brief was a YouTube video; it was pulled apart by hand with yt-dlp and ffmpeg frame sampling and never written down as a file. This skill is that file. - Prompt at 00:39:00Z; `start` could not run until the board existed at 02:09:55Z, so the first turn carries about 91 minutes of thinking. `preBoard` is how to show that hour honestly.-- Four requirements arrived mid-run that intake should have settled: "make sure you make a molecule so it fits into our scaffold", build on our own in-house PCB fab (so Mouser sourcing), a PSpice run matching the brief's workflow, and a scaffold placement for a live probing workcell. The first two are defaults now; the last two belong in the deliverables readback.+- Four requirements arrived mid-run that intake should have settled: "make sure you make a molecule so it fits into our scaffold", build on the 3rd party fab (so Mouser sourcing), a PSpice run matching the brief's workflow, and a scaffold placement for a live probing workcell. The first two are defaults now; the last two belong in the deliverables readback. - The human asked "reproduce" and meant independent design: own parts, own calcs, own layout.

@@ -46,7 +46,7 @@ Wrap the push in `adom-aiflow exec -- python3 tools/clips_subreadme.py ...` so i - **Media paths are repo-root-relative**, even inside `docs/clips.md`: `docs/clips/<stem>-10x.mp4`, `docs/clips/<stem>-sheet.png`. The files viewer prepends `files/` to the ref as written; a path relative to the doc's own folder (`clips/x.mp4`) points at the wrong place. Use the same form for plain links to the action cuts. - **Doc links are relative** (`docs/clips.md` from the README), never absolute URLs. A plain link (not an image or a video `src`) resolves from the doc's own folder, so from `docs/clips.md` the action cut is `[...](clips/<stem>-action.mp4)`; checked on the rendered page, it lands on `files/docs/clips/...`. - **Push only what changed** plus `docs/clips.md`; pushing the whole run folder is slow and bloats the page.-- **Scrub before every push**: the script refuses a payload that names the in-house fab's product or carries an em-dash. Say "our own in-house PCB fab".+- **Scrub before every push**: the script refuses a payload that names the 3rd party fab's product or carries an em-dash. Say "the 3rd party fab". - **Rate limits**: one push per step is fine; do not push in a loop.  ## 4. Overnight runs

@@ -1,7 +1,7 @@ --- name: aiflow-molecule description: >--  Make an adom-aiflow board an Adom molecule that fits the scaffold: the 2 mm grid, the origin at the MP1 (front-left) machine pin, MachinePinMediumShort (1.6 mm pad, 1.2 mm drill) at the corners as MP1 to MP4, MachineContactMedium (1.3 mm pad, 0.78 mm drill) for the signal contacts, footprints from the Adom KiCad Library 1.2.3, the fab-rules profile (in-house default, jlcpcb optional), then STEP export, `step2glb convert --molecule` with its stats gates, and molecule-publish. Medium-pin molecules mount on a LrgMed user scaffold (4 mm medium contact grid, large pins on a 32 mm base grid). Trigger words: aiflow molecule, make it a molecule, fits our scaffold, machine pins, MachinePinMediumShort, MachineContactMedium, MP1, molecule grid, molecule outline, fab rules profile, kicad_dru, molecule conformance, molecule export, step2glb molecule, publish molecule, LrgMed scaffold.+  Make an adom-aiflow board an Adom molecule that fits the scaffold: the 2 mm grid, the origin at the MP1 (front-left) machine pin, MachinePinMediumShort (1.6 mm pad, 1.2 mm drill) at the corners as MP1 to MP4, MachineContactMedium (1.3 mm pad, 0.78 mm drill) for the signal contacts, footprints from the Adom KiCad Library 1.2.3, the fab-rules profile (3rd party fab default, jlcpcb optional), then STEP export, `step2glb convert --molecule` with its stats gates, and molecule-publish. Medium-pin molecules mount on a LrgMed user scaffold (4 mm medium contact grid, large pins on a 32 mm base grid). Trigger words: aiflow molecule, make it a molecule, fits our scaffold, machine pins, MachinePinMediumShort, MachineContactMedium, MP1, molecule grid, molecule outline, fab rules profile, kicad_dru, molecule conformance, molecule export, step2glb molecule, publish molecule, LrgMed scaffold. ---  # aiflow-molecule: a board that drops into the scaffold@@ -37,7 +37,7 @@ The DRC gate uses the board's own `.kicad_dru`, so the fab's limits must be in i  | Profile | Rules file | |---|---|-| `inhouse` (default) | the in-house 2-layer rules file shipped for our own in-house PCB fab (`rules/inhouse-2L.kicad_dru` in the project); design with margin above its minimums. Do not restate its process limits on public pages |+| `fab` (default) | the 3rd party fab 2-layer rules file shipped for the 3rd party fab (`rules/fab-2L.kicad_dru` in the project); design with margin above its minimums. Do not restate its process limits on public pages | | `jlcpcb` | JLCPCB's published 2-layer capabilities as a `.kicad_dru` |  `build_board.py` copies the file beside the board; `start` carries `.kicad_pro` and `.kicad_dru` into the run; the gate needs a native kicad-cli for project rules (`ADOM_AIFLOW_KICAD_CLI=adom-aiflow-kicad-cli-remote`). Put the copper weight you designed for in the spec (`copperUm`, with a note).@@ -73,7 +73,7 @@ Gate on the printed stats before publishing: | `footprint_applied`, `footprint_pins` | `true`, 4 | | `warnings` | none | -Then hand the bundle (STEP, board, every schematic sheet, `.kicad_pro`, custom 3D models, the GLB and the footprint and symbol JSON) to the molecule-publish skill. Publishing is its own reviewed step: check the payload for anything confidential first, and say "our own in-house PCB fab" wherever the fab is named.+Then hand the bundle (STEP, board, every schematic sheet, `.kicad_pro`, custom 3D models, the GLB and the footprint and symbol JSON) to the molecule-publish skill. Publishing is its own reviewed step: check the payload for anything confidential first, and say "the 3rd party fab" wherever the fab is named.  ## 6. Hand off @@ -83,5 +83,5 @@ A locked interface, a rules profile in the board, and after the build a converte  - 28 x 20 mm, MP1 to MP4 at (0,0), (24,0), (0,16), (24,16), all GND. - Contacts on the short edges: J1 VIN (0,12), J2 GND (0,8), J3 EN (0,4); J4 VOUT (24,12), J5 GND (24,8), J6 VMON (24,4). Input on the left, output on the right, each with its own ground.-- Rules: in-house 2-layer profile, 1.6 mm FR4, designed for 0.5 oz outer copper.+- Rules: 3rd party fab 2-layer profile, 1.6 mm FR4, designed for 0.5 oz outer copper. - The Adom library footprints reference their STEP through the plugin manager's path; the project carries copies in `kicad/3d/` so the board renders on any machine.

@@ -36,7 +36,7 @@ Use `adom-aiflow silkscreen-dashboard control --json '{"record":"overview"}' --r  A full placement demonstration starts with no authored labels in the candidate occupancy, then attempts every required label. Reuse text content, native glyph metrics and electrical anchors, not earlier accepted positions. Preserve unresolved attempts and subsequent rework in the event history. Front and back are separate collision/placement passes in one run. Filter candidates, selected labels, leaders and playback events by the active face; never overlay the opposite face during a recording. -Show the active label's native text height in millimetres, including distinct reference/value sizes. Maximize readable size near its physical feature; 0.20 mm is a last-resort in-house fab value, not a default. Prefer short curved leader lines whenever contact/pin association is unclear. Route leaders to the feature's visible rim, keep them off holes, pads, bodies and other text, and verify both faces in the native EDA. Include leaders as actual placement/rework events.+Show the active label's native text height in millimetres, including distinct reference/value sizes. Maximize readable size near its physical feature; 0.20 mm is a last-resort 3rd party fab value, not a default. Prefer short curved leader lines whenever contact/pin association is unclear. Route leaders to the feature's visible rim, keep them off holes, pads, bodies and other text, and verify both faces in the native EDA. Include leaders as actual placement/rework events.  Record each face as a 1920x1080 detailed replay with an explicit replay label. End the review video with the same revision in the user's native EDA, including top and bottom inspection. A dashboard preview or API success is not proof of a faithful native transfer. Keep native raw clips separate from captioned/replayed dashboard clips. 

@@ -1,7 +1,7 @@ --- name: aiflow-sourcing description: >--  Parts and CAD sourcing for an adom-aiflow board, before the schematic is frozen: the fab profile picks where parts come from (default "in-house" = our own in-house PCB fab, Mouser plus Adom stocked basic parts, no JLCPCB parts; user-selectable "jlcpcb" = JLCPCB/LCSC basic parts), search by spec and in stock before naming an MPN, constrain passives to the stocked set, record stock and lead time with a date, then get each part's symbol, footprint and STEP in a fixed order (manufacturer site, distributor CAD links, Adom wiki component page, draw your own labelled AI-generated) and check every model on the step2glb service. Never adom-chipsmith. Trigger words: aiflow sourcing, source the BOM, pick parts, in stock, lead time, sourcing profile, fab profile, Mouser or JLCPCB, Adom basic parts, stocked values, find the STEP, 3D model for this part, manufacturer CAD, SamacSys, Ultra Librarian, footprint source, symbol source.+  Parts and CAD sourcing for an adom-aiflow board, before the schematic is frozen: the fab profile picks where parts come from (default "3rd party fab" = the 3rd party fab, Mouser plus Adom stocked basic parts, no JLCPCB parts; user-selectable "jlcpcb" = JLCPCB/LCSC basic parts), search by spec and in stock before naming an MPN, constrain passives to the stocked set, record stock and lead time with a date, then get each part's symbol, footprint and STEP in a fixed order (manufacturer site, distributor CAD links, Adom wiki component page, draw your own labelled AI-generated) and check every model on the step2glb service. Never adom-chipsmith. Trigger words: aiflow sourcing, source the BOM, pick parts, in stock, lead time, sourcing profile, fab profile, Mouser or JLCPCB, Adom basic parts, stocked values, find the STEP, 3D model for this part, manufacturer CAD, SamacSys, Ultra Librarian, footprint source, symbol source. ---  # aiflow-sourcing: parts that exist, CAD that is true@@ -14,14 +14,14 @@ Read `fab.target` from requirements.json (aiflow-intake) and set `sourcing.profi  | Profile | When | Parts come from | Never | |---|---|---|---|-| `inhouse` (default) | Our own in-house PCB fab | Adom stocked basic parts (the pick-and-place reels) first, then Mouser | JLCPCB/LCSC-only parts |+| `fab` (default) | The 3rd party fab | Adom stocked basic parts (the pick-and-place reels) first, then Mouser | JLCPCB/LCSC-only parts | | `jlcpcb` (user choice) | The human picks a JLCPCB build | JLCPCB/LCSC basic parts first, extended only with a reason | parts JLCPCB cannot place | -Switching profile redoes this whole pass; never mix profiles in one BOM. A thin-stock IC on the in-house profile is a note and an early order, not a reason to switch to JLCPCB parts.+Switching profile redoes this whole pass; never mix profiles in one BOM. A thin-stock IC on the 3rd party fab profile is a note and an early order, not a reason to switch to JLCPCB parts.  ## 2. Passives: the stocked set first -On `inhouse`, every R, C, LED and small magnetic that Adom stocks comes from the reels. The math bends to the stock, not the other way round (aiflow-circuit-design searches the combinations).+On `fab`, every R, C, LED and small magnetic that Adom stocks comes from the reels. The math bends to the stock, not the other way round (aiflow-circuit-design searches the combinations).  ```bash pnp-inventory lookup "10k 0402"                          # match to a stocked MPN@@ -92,7 +92,7 @@ step2glb thumbnail part.step       # look at it ## Worked example: TPS54202 molecule (stock checked 2026-09-29)  - Remembered first picks had zero Mouser stock: Coilcraft XAL5050-153MEC (280-day lead) and Murata GRM31CR71E106KA12L (182-day lead). The spec search found Abracon AMPLH5030S-150MT (1577 in stock) and Yageo CC1206KKX7R8BB106 (18168) at once.-- TPS54202DDCR: Mouser 160, 140-day lead; DigiKey 0; JLCPCB about 180k. On the in-house profile that is a thin-stock note, not a profile switch.+- TPS54202DDCR: Mouser 160, 140-day lead; DigiKey 0; JLCPCB about 180k. On the 3rd party fab profile that is a thin-stock note, not a profile switch. - The 41-value resistor set had no single feedback-top value; calcs.py chose 68k + 5.6k in series. - The inductor was first drawn from the datasheet with a local OCCT install before looking properly; Abracon's official STEP turned up only when searching the series `AMPLH5030S`. Panasonic publishes electrolytic STEPs by case (`DS_Alumi_D_5.zip`), and that search caught a case size written into the BOM from memory (the page says 6.3 x 5.8 mm, case D). Search first, draw last. - Three models were Y-up and needed -90 X: Abracon AMPLH5030S, Panasonic case D, and the wiki's Samsung CL21A226MPQNNNE 0805. `step2glb features` showed it.

@@ -30,7 +30,7 @@ Use `adom-aiflow silkscreen-dashboard control --json '{"record":"overview"}' --r  A full placement demonstration starts with no authored labels in the candidate occupancy, then attempts every required label. Reuse text content, native glyph metrics and electrical anchors, not earlier accepted positions. Preserve unresolved attempts and subsequent rework in the event history. Front and back are separate collision/placement passes in one run. Filter candidates, selected labels, leaders and playback events by the active face; never overlay the opposite face during a recording. -Show the active label's native text height in millimetres, including distinct reference/value sizes. Maximize readable size near its physical feature; 0.20 mm is a last-resort in-house fab value, not a default. Prefer short curved leader lines whenever contact/pin association is unclear. Route leaders to the feature's visible rim, keep them off holes, pads, bodies and other text, and verify both faces in the native EDA. Include leaders as actual placement/rework events.+Show the active label's native text height in millimetres, including distinct reference/value sizes. Maximize readable size near its physical feature; 0.20 mm is a last-resort 3rd party fab value, not a default. Prefer short curved leader lines whenever contact/pin association is unclear. Route leaders to the feature's visible rim, keep them off holes, pads, bodies and other text, and verify both faces in the native EDA. Include leaders as actual placement/rework events.  Record each face as a 1920x1080 detailed replay with an explicit replay label. End the review video with the same revision in the user's native EDA, including top and bottom inspection. A dashboard preview or API success is not proof of a faithful native transfer. Keep native raw clips separate from captioned/replayed dashboard clips.