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AD7928BRUZ-REEL7

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Analog Devices Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7928BRUZ-REEL7

Analog Devices · Analog To Digital Converters (ADC) · TSSOP-20

AD7928BRUZ-REEL7 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock logic input that provides the serial clock for accessing data and is also the master clock for the conversion process.
2 DIN input Data in logic input; data written to the control register is clocked in on the falling edge of SCLK.
3 CS input Active-low chip select logic input that initiates conversions, samples the input on its falling edge, and frames the serial data transfer.
4 AGND power_in Analog ground reference point for all analog circuitry; all AGND pins should be connected together.
5 AVDD power_in Analog power supply input, 2.7 V to 5.25 V; for the 0 V to 2 × REFIN input range AVDD must be 4.75 V to 5.25 V.
6 AVDD power_in Analog power supply input, 2.7 V to 5.25 V; for the 0 V to 2 × REFIN input range AVDD must be 4.75 V to 5.25 V.
7 REFIN input External reference input that must be driven with 2.5 V ±1% for specified performance.
8 AGND power_in Analog ground reference point for all analog circuitry; all AGND pins should be connected together.
9 VIN7 input Single-ended analog input channel 7 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
10 VIN6 input Single-ended analog input channel 6 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
11 VIN5 input Single-ended analog input channel 5 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
12 VIN4 input Single-ended analog input channel 4 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
13 VIN3 input Single-ended analog input channel 3 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
14 VIN2 input Single-ended analog input channel 2 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
15 VIN1 input Single-ended analog input channel 1 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
16 VIN0 input Single-ended analog input channel 0 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND.
17 AGND power_in Analog ground reference point for all analog circuitry; all AGND pins should be connected together.
18 DOUT output Serial data output that clocks out the conversion result MSB first on the falling edge of SCLK, preceded by a leading zero and three channel address bits.
19 VDRIVE power_in Logic power supply input that sets the voltage levels of the serial interface, independent of AVDD.
20 AGND power_in Analog ground reference point for all analog circuitry; all AGND pins should be connected together.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category Data Acquisition
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral linearity error (ordering guide grade for AD7928BRUZ-REEL7) -1 1 LSB Ordering Guide ±1 LSB linearity (integral) for AD7928 B grade, -40 C to +85 C 28
AVDD supply voltage AVDD 2.7 5.25 V Pin description: AVDD range 2.7 V to 5.25 V 11
AVDD supply voltage for 0 V to 2 x REFIN range AVDD 4.75 5.25 V 0 V to 2 x REFIN input range 11
REFIN external reference voltage REFIN 2.5 V Specified performance 11
REFIN reference voltage tolerance REFIN -1 1 % 2.5 V ±1% for specified performance 11
SCLK frequency fSCLK 10 kHz AVDD = 3 V and 5 V; tr = tf = 5 ns; TMIN to TMAX 9
SCLK frequency fSCLK 20 MHz AVDD = 3 V and 5 V; tr = tf = 5 ns; TMIN to TMAX 9
Quiet time between CS rising edge and next conversion start tQUIET 50 ns AVDD = 3 V and 5 V; tr = tf = 5 ns; TMIN to TMAX 9
CS to SCLK setup time t2 10 ns AVDD = 3 V and 5 V; tr = tf = 5 ns; TMIN to TMAX 9
Delay from CS until DOUT three-state disabled t3 35 ns AVDD = 3 V; load circuit Figure 2 9
Delay from CS until DOUT three-state disabled t3 30 ns AVDD = 5 V; load circuit Figure 2 9
Data access time after SCLK falling edge t4 40 ns AVDD = 3 V; load circuit Figure 2 9
SCLK to DOUT valid hold time t7 10 ns AVDD = 3 V and 5 V; tr = tf = 5 ns 9
SCLK falling edge to DOUT high impedance t8 15 45 ns AVDD = 3 V; extrapolated bus relinquish time 9
SCLK falling edge to DOUT high impedance t8 15 35 ns AVDD = 5 V; extrapolated bus relinquish time 9
DIN setup time prior to SCLK falling edge t9 10 ns AVDD = 3 V and 5 V; tr = tf = 5 ns 9
DIN hold time after SCLK falling edge t10 5 ns AVDD = 3 V and 5 V; tr = tf = 5 ns 9
16th SCLK falling edge to CS high t11 20 ns AVDD = 3 V and 5 V; tr = tf = 5 ns 9
Power-up time from full power-down/auto shutdown mode t12 1 μs AVDD = 3 V and 5 V 9
AVDD to AGND AVDD -0.3 7 V TA = 25 C 10
VDRIVE to AGND VDRIVE -0.3 V Upper limit printed as AVDD + 0.3 V; TA = 25 C 10
Analog input voltage to AGND VIN -0.3 V Upper limit printed as AVDD + 0.3 V; TA = 25 C 10
Digital input voltage to AGND -0.3 7 V TA = 25 C 10
Digital output voltage to AGND -0.3 V Upper limit printed as AVDD + 0.3 V; TA = 25 C 10
REFIN to AGND REFIN -0.3 V Upper limit printed as AVDD + 0.3 V; TA = 25 C 10
Input current to any pin except supplies -10 10 mA Transient currents up to 100 mA do not cause SCR latch-up 10
Operating temperature range (B version) TA -40 85 C Commercial B version 10
Storage temperature range -65 150 C 10
Junction temperature TJ 150 C 10
TSSOP package power dissipation 450 mW TSSOP package 10
Lead temperature, vapor phase soldering 215 C 60 s 10
Lead temperature, infrared soldering 220 C 15 s 10
ESD rating 1.5 kV Test model not stated 10
Thermal impedance junction to ambient (TSSOP) θJA 143 °C/W TSSOP package 10
Thermal impedance junction to case (TSSOP) θJC 45 °C/W TSSOP package 10

CAD (KiCad official)

  • Symbol: AD7928BRUZ-REEL7
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad7928bruz-reel7-etched.step / ad7928bruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7928bruz-reel7.step / ad7928bruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 8d3a9b226094694a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF