AD7928BRUZ-REEL7

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  "title": "AD7928BRUZ-REEL7",
  "brief": "Analog Devices Analog To Digital Converters (ADC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "mpn": "AD7928BRUZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-20",
    "pin_count": 20,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
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      "lcsc": "C183018",
      "digikey": "AD7928BRUZ-REEL7TR-ND",
      "mouser": "584-AD7928BRUZ-R7"
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      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock logic input that provides the serial clock for accessing data and is also the master clock for the conversion process."
      },
      {
        "number": "2",
        "name": "DIN",
        "type": "input",
        "description": "Data in logic input; data written to the control register is clocked in on the falling edge of SCLK."
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      {
        "number": "3",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select logic input that initiates conversions, samples the input on its falling edge, and frames the serial data transfer."
      },
      {
        "number": "4",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground reference point for all analog circuitry; all AGND pins should be connected together."
      },
      {
        "number": "5",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog power supply input, 2.7 V to 5.25 V; for the 0 V to 2 × REFIN input range AVDD must be 4.75 V to 5.25 V."
      },
      {
        "number": "6",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog power supply input, 2.7 V to 5.25 V; for the 0 V to 2 × REFIN input range AVDD must be 4.75 V to 5.25 V."
      },
      {
        "number": "7",
        "name": "REFIN",
        "type": "input",
        "description": "External reference input that must be driven with 2.5 V ±1% for specified performance."
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      {
        "number": "8",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground reference point for all analog circuitry; all AGND pins should be connected together."
      },
      {
        "number": "9",
        "name": "VIN7",
        "type": "input",
        "description": "Single-ended analog input channel 7 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND."
      },
      {
        "number": "10",
        "name": "VIN6",
        "type": "input",
        "description": "Single-ended analog input channel 6 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND."
      },
      {
        "number": "11",
        "name": "VIN5",
        "type": "input",
        "description": "Single-ended analog input channel 5 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND."
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      {
        "number": "12",
        "name": "VIN4",
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        "number": "13",
        "name": "VIN3",
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        "name": "VIN2",
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        "number": "15",
        "name": "VIN1",
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        "description": "Single-ended analog input channel 1 multiplexed into the track-and-hold; input range 0 V to REFIN or 0 V to 2 × REFIN, and unused inputs must be tied to AGND."
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        "name": "VIN0",
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      {
        "number": "17",
        "name": "AGND",
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        "description": "Analog ground reference point for all analog circuitry; all AGND pins should be connected together."
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      {
        "number": "18",
        "name": "DOUT",
        "type": "output",
        "description": "Serial data output that clocks out the conversion result MSB first on the falling edge of SCLK, preceded by a leading zero and three channel address bits."
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