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AD5689RARUZ-RL7

Analog Devices · Digital To Analog Converters (DAC) · TSSOP-16

AD5689RARUZ-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	power_in	Reference voltage pin, which is the reference output when the internal reference is used and the reference input when an external reference is used; the default is reference output.
2	NC	unconnected	No connect; do not connect to this pin.
3	VOUTA	output	Analog output voltage from DAC A, with rail-to-rail output amplifier operation.
4	GND	power_in	Ground reference point for all circuitry on the device.
5	VDD	power_in	Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
6	NC	unconnected	No connect; do not connect to this pin.
7	VOUTB	output	Analog output voltage from DAC B, with rail-to-rail output amplifier operation.
8	SDO	output	Serial data output used for daisy-chaining devices or for readback, with data transferred on the SCLK rising edge and valid on the falling edge.
9	LDAC	input	Load DAC input operating asynchronously or synchronously; pulsing low updates either or both DAC registers when new input data is present, and the pin may be tied permanently low.
10	GAIN	input	Gain select; tying to GND gives a 0 V to VREF output span and tying to VLOGIC gives a 0 V to 2 × VREF span.
11	VLOGIC	power_in	Digital power supply with a voltage range of 1.62 V to 5.5 V.
12	SCLK	input	Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz.
13	SYNC	input	Active-low frame synchronization input; when SYNC goes low, data is transferred in on the falling edges of the next 24 clocks.
14	SDIN	input	Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK.
15	RESET	input	Asynchronous, falling-edge-sensitive active-low reset that clears both DACs to zero scale or midscale per RSTSEL and must be kept low for a minimum time; LDAC pulses are ignored while low.
16	RSTSEL	input	Power-on reset select; tying to GND powers both DACs up to zero scale and tying to VLOGIC powers both DACs up to midscale.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Data Acquisition
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (INL), Gain = 2	INL	-8	2	8	LSB	Gain = 2	3
Relative Accuracy (INL), Gain = 1	INL	-8	2	8	LSB	Gain = 1	3
Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed monotonic by design	3
Zero-Code Error			0.4	4	mV	All 0s loaded to DAC register	3
Offset Error		-4	0.1	4	mV		3
Full-Scale Error		-0.2	0.01	0.2	% of FSR	All 1s loaded to DAC register	3
Gain Error		-0.2	0.02	0.2	% of FSR		3
Total Unadjusted Error		-0.25	0.01	0.25	% of FSR	External reference; gain = 2; TSSOP	3
Offset Error Drift		-1		1	µV/°C		3
Gain Temperature Coefficient		-1		1	ppm Of FSR/°C		3
DC Power Supply Rejection Ratio				0.15	mV/V	DAC code = midscale; VDD = 5 V ± 10%	3
DC Crosstalk due to single channel full-scale output change		-2		2	µV	Due to single channel, full-scale output change	3
DC Crosstalk due to load current change		-3		3	µV/mA	Due to load current change	3
DC Crosstalk due to powering down (per channel)		-2		2	µV	Due to powering down (per channel)	3
Output Voltage Range, Gain = 1	VOUT	0			V	Gain = 1	3
Output Voltage Range, Gain = 2	VOUT	0			V	Gain = 2, see Figure 31	3
Capacitive Load Stability				2	nF	RL = ∞	3
Capacitive Load Stability				10	nF	RL = 1 kΩ	3
Resistive Load	RL	1			kΩ		3
Load Regulation, 5 V supply				80	µV/mA	5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA	3
Load Regulation, 3 V supply				80	µV/mA	3 V ± 10%, DAC code = midscale; −20 mA ≤ IOUT ≤ 20 mA	3
Reference Output Voltage		2.4975		2.5025	V	At ambient	4
Reference Temperature Coefficient (A grade)			5	20	ppm/°C		4
Input Low Voltage	VINL			0.3	× VLOGIC		4
Input High Voltage	VINH	0.7			× VLOGIC		4
Input Current		-2		2	µA	Per pin	4
Output Low Voltage (SDO)	VOL			0.4	V	ISINK = 200 μA	4
VDD, Gain = 1	VDD	2.7		5.5	V	Gain = 1	4
VDD, Gain = 2	VDD			5.5	V	Gain = 2	4
VLOGIC	VLOGIC	1.62		5.5	V		4
Logic Supply Current	ILOGIC			3	µA		4
Normal Mode Supply Current, internal reference off	IDD		0.59	0.7	mA	VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off	4
Normal Mode Supply Current, internal reference on at full scale	IDD		1.1	1.3	mA	VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference on, at full scale	4
All Power-Down Modes Supply Current	IDD		1	4	µA	−40°C to +85°C	4
All Power-Down Modes Supply Current	IDD			6	µA	−40°C to +105°C	4
Output Voltage Settling Time (AD5689R)			5	8	µs	¼ to ¾ scale settling to ±2 LSB	5
VDD to GND	VDD	-0.3		7	V		9
VLOGIC to GND	VLOGIC	-0.3		7	V		9
Operating Temperature Range		-40		105	°C		9
Storage Temperature Range		-65		150	°C		9
Junction Temperature				125	°C		9
16-Lead TSSOP θJA Thermal Impedance	θJA		112.6		°C/W	0 Airflow (4-Layer Board)	9
SCLK Cycle Time	t1	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK High Time	t2	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Low Time	t3	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC to SCLK Falling Edge Setup Time	t4	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Setup Time	t5	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Data Hold Time	t6	5			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SCLK Falling Edge to SYNC Rising Edge	t7	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Minimum SYNC High Time	t8	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates)	t9	830			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Falling Edge to SCLK Fall Ignore	t10	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Pulse Width Low	t11	15			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Rising Edge	t12	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
SYNC Rising Edge to LDAC Falling Edge	t13	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
LDAC Falling Edge to SYNC Rising Edge	t14	800			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Minimum Pulse Width Low	t15	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Pulse Activation Time	t16	30			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	6
Power-Up Time				4.5	µs	2.7 V ≤ VLOGIC ≤ 5.5 V	6

CAD (KiCad official)

Symbol: AD5689RARUZ-RL7
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5689raruz-rl7-etched.step / ad5689raruz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5689raruz-rl7.step / ad5689raruz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 130e141a164421b7, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF