AD5685RBCPZ-RL7

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  "title": "AD5685RBCPZ-RL7",
  "brief": "Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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    "manufacturer": "Analog Devices",
    "package": "LFCSP-16(3x3)",
    "pin_count": 17,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
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      "lcsc": "C650098",
      "digikey": "505-AD5685RBCPZ-RL7TR-ND",
      "mouser": "584-AD5685RBCPZ-R7"
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      {
        "number": "1",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A; the output amplifier has rail-to-rail operation."
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      {
        "number": "2",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
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      {
        "number": "3",
        "name": "VDD",
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        "description": "Power supply input operated from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
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      {
        "number": "4",
        "name": "VOUTC",
        "type": "output",
        "description": "Analog output voltage from DAC C; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "5",
        "name": "VOUTD",
        "type": "output",
        "description": "Analog output voltage from DAC D; the output amplifier has rail-to-rail operation."
      },
      {
        "number": "6",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output used for daisy-chaining devices or for readback, transferred on the rising edge of SCLK and valid on the falling edge."
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      {
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        "name": "LDAC",
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        "description": "Load DAC control that, when pulsed low, updates any or all DAC registers with new input data, and can be tied permanently low."
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      {
        "number": "8",
        "name": "GAIN",
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        "description": "Span set pin: tied to GND gives a 0 V to VREF output span, tied to VLOGIC gives a 0 V to 2 × VREF span on all four DACs."
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        "number": "10",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz."
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      {
        "number": "11",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks."
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        "number": "12",
        "name": "SDIN",
        "type": "input",
        "description": "Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK."
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        "number": "13",
        "name": "RESET",
        "type": "input",
        "description": "Falling-edge-sensitive asynchronous reset input that loads zero scale or midscale per RSTSEL and ignores LDAC pulses while low."
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        "number": "14",
        "name": "RSTSEL",
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        "description": "Power-on reset select: tied to GND powers all four DACs to zero scale, tied to VLOGIC powers all four DACs to midscale."
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        "name": "VREF",
        "type": "power_in",
        "description": "Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used; the default is reference output."
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      "Package": "LFCSP-16(3x3)",
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