component
AD5685RBCPZ-RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD5685RBCPZ-RL7
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)
AD5685RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input operated from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTC | output | Analog output voltage from DAC C; the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D; the output amplifier has rail-to-rail operation. |
| 6 | SDO | output | Serial data output used for daisy-chaining devices or for readback, transferred on the rising edge of SCLK and valid on the falling edge. |
| 7 | LDAC | input | Load DAC control that, when pulsed low, updates any or all DAC registers with new input data, and can be tied permanently low. |
| 8 | GAIN | input | Span set pin: tied to GND gives a 0 V to VREF output span, tied to VLOGIC gives a 0 V to 2 × VREF span on all four DACs. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range from 1.8 V to 5.5 V. |
| 10 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz. |
| 11 | SYNC | input | Active-low frame synchronization input; when low, data is transferred in on the falling edges of the next 24 clocks. |
| 12 | SDIN | input | Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK. |
| 13 | RESET | input | Falling-edge-sensitive asynchronous reset input that loads zero scale or midscale per RSTSEL and ignores LDAC pulses while low. |
| 14 | RSTSEL | input | Power-on reset select: tied to GND powers all four DACs to zero scale, tied to VLOGIC powers all four DACs to midscale. |
| 15 | VREF | power_in | Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used; the default is reference output. |
| 16 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 17 | EPAD | power_in | Exposed pad that must be tied to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | INL | 0.5 | 1 | LSB | 3 | ||
| Differential Nonlinearity | DNL | 1 | LSB | Guaranteed monotonic by design | 3 | ||
| Zero-Code Error | 0.4 | 1.5 | mV | All zeros loaded to DAC register | 3 | ||
| Offset Error | -1.5 | 0.1 | 1.5 | mV | 3 | ||
| Full-Scale Error | -0.1 | 0.01 | 0.1 | % of FSR | All ones loaded to DAC register | 3 | |
| Gain Error | -0.1 | 0.02 | 0.1 | % of FSR | 3 | ||
| Offset Error Drift | -1 | 1 | µV/°C | 3 | |||
| Gain Temperature Coefficient | -1 | 1 | ppm of FSR/°C | 3 | |||
| Resistive Load | RL | 1 | kΩ | 3 | |||
| Reference Output Voltage | VREF | 2.4975 | 2.5025 | V | At ambient | 3 | |
| Reference Temperature Coefficient | TC | 2 | 5 | ppm/°C | See the Terminology section | 3 | |
| Supply Voltage VDD (Gain = 1) | VDD | 2.7 | 5.5 | V | Gain = 1 | 3 | |
| Logic Supply Voltage | VLOGIC | 1.62 | 5.5 | V | 3 | ||
| Normal Mode Supply Current | IDD | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off | 4 | |
| Normal Mode Supply Current, Internal Reference On | IDD | 1.1 | 1.3 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference on, at full scale | 4 | |
| All Power-Down Modes Supply Current | IDD | 1 | 4 | µA | −40°C to +85°C | 4 | |
| All Power-Down Modes Supply Current, High Temperature | IDD | 6 | µA | −40°C to +105°C | 4 | ||
| Output Voltage Settling Time | tS | 5 | 8 | µs | ¼ to ¾ scale settling to ±2 LSB | 5 | |
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| VLOGIC to GND | VLOGIC | -0.3 | 7 | V | 8 | ||
| Operating Temperature Range | TA | -40 | 105 | °C | 8 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 8 | ||
| Junction Temperature | TJ | 125 | °C | 8 | |||
| Reflow Soldering Peak Temperature, Pb Free | 260 | °C | J-STD-020 | 8 | |||
| 16-Lead LFCSP Thermal Impedance, Junction-to-Ambient | θJA | 70 | °C/W | 0 Airflow, 4-Layer Board | 8 |
CAD (KiCad official)
- Symbol:
AD5685RBCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5685rbcpz-rl7-etched.step/ad5685rbcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5685rbcpz-rl7.step/ad5685rbcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (29 pp, sha256
16c7cb655e87649e, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).