component
AD5668BRUZ-2REEL7
Public Made by Adomby adom
ADI(亚德诺) , TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD5668BRUZ-2REEL7
ADI(亚德诺) · IC · TSSOP-16
AD5668BRUZ-2REEL7 from ADI(亚德诺), in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LDAC | input | Pulsing this pin low updates any or all DAC registers whose input registers hold new data, so all outputs update simultaneously; it can alternatively be tied permanently low. |
| 2 | SYNC | input | Active-low frame synchronization input that enables the input shift register, with data clocked in on the falling edges of the next 32 clocks, and a rising edge before the 32nd falling edge aborts the write. |
| 3 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTA | output | Analog output voltage from DAC A with a rail-to-rail output amplifier. |
| 5 | VOUTC | output | Analog output voltage from DAC C with a rail-to-rail output amplifier. |
| 6 | VOUTE | output | Analog output voltage from DAC E with a rail-to-rail output amplifier. |
| 7 | VOUTG | output | Analog output voltage from DAC G with a rail-to-rail output amplifier. |
| 8 | VREFIN/VREFOUT | bidirectional | Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input. |
| 9 | CLR | input | Falling-edge-sensitive asynchronous clear input that loads the CLR code register value (zero, midscale or full scale) into the DAC registers, with LDAC pulses ignored while low and defaulting to clearing the output to 0 V. |
| 10 | VOUTH | output | Analog output voltage from DAC H with a rail-to-rail output amplifier. |
| 11 | VOUTF | output | Analog output voltage from DAC F with a rail-to-rail output amplifier. |
| 12 | VOUTD | output | Analog output voltage from DAC D with a rail-to-rail output amplifier. |
| 13 | VOUTB | output | Analog output voltage from DAC B with a rail-to-rail output amplifier. |
| 14 | GND | power_in | Ground reference point for all circuitry on the part. |
| 15 | DIN | input | Serial data input to a 32-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 16 | SCLK | input | Serial clock input that clocks data into the input shift register on its falling edge at rates of up to 50 MHz. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ADI(亚德诺) |
| Package | TSSOP-16 |
| Category | |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | -16 | 8 | 16 | LSB | See Figure 7 | 4 | |
| Zero-Code Error | 6 | 19 | mV | All 0s loaded to DAC register (see Figure 26) | 4 | ||
| Offset Error | 6 | 19 | mV | 4 | |||
| Full-Scale Error | -0.2 | -1 | % FSR | All 1s loaded to DAC register (see Figure 27) | 4 | ||
| Gain Error | -1 | 1 | % FSR | 4 | |||
| Gain Temperature Coefficient | -2.5 | 2.5 | ppm Of FSR/°C | 4 | |||
| Zero-Code Error Drift | -2 | 2 | µV/°C | 4 | |||
| Differential Nonlinearity | -1 | 1 | LSB | Guaranteed monotonic by design (see Figure 10) | 4 | ||
| Reference Output Voltage | 2.495 | 2.505 | V | AD5668-2, AD5668-3; at ambient | 4 | ||
| Reference Current | 40 | 55 | µA | VREF = VDD = 5.5 V (per DAC channel) | 4 | ||
| Input Current | -3 | 3 | µA | All digital inputs | 5 | ||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V | 5 | ||
| Input High Voltage | VINH | 2 | V | VDD = 5 V | 5 | ||
| VDD | VDD | 4.5 | 5.5 | V | All digital inputs at 0 or VDD, DAC active, excludes load current | 5 | |
| IDD (Normal Mode), internal reference off | IDD | 1 | 1.5 | mA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference off | 5 | |
| IDD (Normal Mode), internal reference on | IDD | 1.7 | 2.25 | mA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference on | 5 | |
| IDD (All Power-Down Modes) | IDD | 0.4 | 1 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND | 5 | |
| DC Power Supply Rejection Ratio | PSRR | -80 | dB | VDD ± 10% | 4 | ||
| DC Crosstalk (External Reference), full-scale output change | 10 | µV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk (External Reference), load current change | 5 | µV/mA | Due to load current change | 4 | |||
| DC Crosstalk (External Reference), powering down | 10 | µV | Due to powering down (per channel) | 4 | |||
| DC Crosstalk (Internal Reference), full-scale output change | 25 | µV | Due to full-scale output change, RL = 2 kΩ to GND or VDD | 4 | |||
| DC Crosstalk (Internal Reference), load current change | 10 | µV/mA | Due to load current change | 4 | |||
| Output Voltage Range | VOUT | 0 | V | Upper limit printed as VDD | 4 | ||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 4 | |||
| Capacitive Load Stability | 10 | nF | RL = 2 kΩ | 4 | |||
| DC Output Impedance | 0.5 | Ω | 4 | ||||
| Short-Circuit Current | 30 | mA | VDD = 5 V | 4 | |||
| Power-Up Time | 4 | µs | Coming out of power-down mode, VDD = 5 V | 4 | |||
| Reference Input Impedance | 14.6 | kΩ | 4 | ||||
| Reference TC | 5 | 10 | ppm/°C | TSSOP | 4 | ||
| Reference Output Impedance | 7.5 | kΩ | 4 | ||||
| Pin Capacitance | 3 | pF | 5 | ||||
| Output Voltage Settling Time | 2.5 | 7 | µs | ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) | 7 | ||
| Slew Rate | 1.2 | V/µs | 7 | ||||
| Resolution | 16 | Bits | AD5668 | 4 | |||
| Supply Voltage (recommended operating range) | VDD | 2.7 | 5.5 | V | Single power supply, 2.7 V to 5.5 V | 1 | |
| Operating Temperature Range (Industrial) | -40 | 105 | °C | Industrial | 9 | ||
| VDD to GND | VDD | -0.3 | 7 | V | Referenced to GND | 9 | |
| VOUT to GND | VOUT | -0.3 | V | Upper limit printed as VDD + 0.3 V | 9 | ||
| Storage Temperature Range | -65 | 150 | °C | 9 | |||
| Junction Temperature (TJ MAX) | TJ | 150 | °C | 9 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Pb Free | 9 | |||
| Thermal Resistance Junction-to-Ambient (RU-16) | θJA | 113.5 | °C/W | JEDEC 2S2P thermal test board | 9 | ||
| Thermal Resistance Junction-to-Case (RU-16) | θJC | 35 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
AD5668BRUZ-2REEL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad5668bruz-2reel7-etched.step/ad5668bruz-2reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5668bruz-2reel7.step/ad5668bruz-2reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ADI(亚德诺) datasheet (30 pp, sha256
aa0519e5e63a0198, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).