component
AD5668BRUZ-2REEL7
Public Made by Adomby adom
ADI(亚德诺) , TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
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"description": "ADI(亚德诺) , TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"component": {
"mpn": "AD5668BRUZ-2REEL7",
"manufacturer": "ADI(亚德诺)",
"package": "TSSOP-16",
"pin_count": 16,
"category": "IC",
"subcategory": "IC",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf",
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"lbr": "ad5668bruz-2reel7.lbr"
},
"distributor_links": {
"lcsc": "C578267",
"digikey": "AD5668BRUZ-2REEL7TR-ND",
"mouser": "584-AD5668BRUZ-2R7"
},
"distributor_check": {
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"source": "Component Ocean /api/assign-pns",
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},
"pins": [
{
"number": "1",
"name": "LDAC",
"type": "input",
"description": "Pulsing this pin low updates any or all DAC registers whose input registers hold new data, so all outputs update simultaneously; it can alternatively be tied permanently low."
},
{
"number": "2",
"name": "SYNC",
"type": "input",
"description": "Active-low frame synchronization input that enables the input shift register, with data clocked in on the falling edges of the next 32 clocks, and a rising edge before the 32nd falling edge aborts the write."
},
{
"number": "3",
"name": "VDD",
"type": "power_in",
"description": "Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
},
{
"number": "4",
"name": "VOUTA",
"type": "output",
"description": "Analog output voltage from DAC A with a rail-to-rail output amplifier."
},
{
"number": "5",
"name": "VOUTC",
"type": "output",
"description": "Analog output voltage from DAC C with a rail-to-rail output amplifier."
},
{
"number": "6",
"name": "VOUTE",
"type": "output",
"description": "Analog output voltage from DAC E with a rail-to-rail output amplifier."
},
{
"number": "7",
"name": "VOUTG",
"type": "output",
"description": "Analog output voltage from DAC G with a rail-to-rail output amplifier."
},
{
"number": "8",
"name": "VREFIN/VREFOUT",
"type": "bidirectional",
"description": "Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input."
},
{
"number": "9",
"name": "CLR",
"type": "input",
"description": "Falling-edge-sensitive asynchronous clear input that loads the CLR code register value (zero, midscale or full scale) into the DAC registers, with LDAC pulses ignored while low and defaulting to clearing the output to 0 V."
},
{
"number": "10",
"name": "VOUTH",
"type": "output",
"description": "Analog output voltage from DAC H with a rail-to-rail output amplifier."
},
{
"number": "11",
"name": "VOUTF",
"type": "output",
"description": "Analog output voltage from DAC F with a rail-to-rail output amplifier."
},
{
"number": "12",
"name": "VOUTD",
"type": "output",
"description": "Analog output voltage from DAC D with a rail-to-rail output amplifier."
},
{
"number": "13",
"name": "VOUTB",
"type": "output",
"description": "Analog output voltage from DAC B with a rail-to-rail output amplifier."
},
{
"number": "14",
"name": "GND",
"type": "power_in",
"description": "Ground reference point for all circuitry on the part."
},
{
"number": "15",
"name": "DIN",
"type": "input",
"description": "Serial data input to a 32-bit shift register, with data clocked in on the falling edge of the serial clock."
},
{
"number": "16",
"name": "SCLK",
"type": "input",
"description": "Serial clock input that clocks data into the input shift register on its falling edge at rates of up to 50 MHz."
}
],
"provenance": {
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"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
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"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
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"at": "2026-11-02T16:54:37"
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"datasheet": {
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"pages": 30,
"sha256": "aa0519e5e63a0198",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
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