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Ray Set visibility: public 47e385d 23h ago
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{
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  "type": "component",
  "slug": "ad5668bruz-2reel7",
  "title": "AD5668BRUZ-2REEL7",
  "brief": "ADI(亚德诺) , TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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    "mpn": "AD5668BRUZ-2REEL7",
    "manufacturer": "ADI(亚德诺)",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "IC",
    "subcategory": "IC",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf",
    "parts": {
      "symbol": "ad5668bruz-2reel7.kicad_sym",
      "footprint": "ad5668bruz-2reel7.kicad_mod",
      "model_3d": "ad5668bruz-2reel7-hero.glb",
      "model_3d_plain": "ad5668bruz-2reel7-etched.glb",
      "model_3d_step": "ad5668bruz-2reel7-etched.step",
      "model_3d_step_plain": "ad5668bruz-2reel7.step",
      "lbr": "ad5668bruz-2reel7.lbr"
    },
    "distributor_links": {
      "lcsc": "C578267",
      "digikey": "AD5668BRUZ-2REEL7TR-ND",
      "mouser": "584-AD5668BRUZ-2R7"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T16:54:48Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD5668BRUZ-2REEL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD5668BRUZ-2R7",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "LDAC",
        "type": "input",
        "description": "Pulsing this pin low updates any or all DAC registers whose input registers hold new data, so all outputs update simultaneously; it can alternatively be tied permanently low."
      },
      {
        "number": "2",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input that enables the input shift register, with data clocked in on the falling edges of the next 32 clocks, and a rising edge before the 32nd falling edge aborts the write."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "4",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A with a rail-to-rail output amplifier."
      },
      {
        "number": "5",
        "name": "VOUTC",
        "type": "output",
        "description": "Analog output voltage from DAC C with a rail-to-rail output amplifier."
      },
      {
        "number": "6",
        "name": "VOUTE",
        "type": "output",
        "description": "Analog output voltage from DAC E with a rail-to-rail output amplifier."
      },
      {
        "number": "7",
        "name": "VOUTG",
        "type": "output",
        "description": "Analog output voltage from DAC G with a rail-to-rail output amplifier."
      },
      {
        "number": "8",
        "name": "VREFIN/VREFOUT",
        "type": "bidirectional",
        "description": "Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input."
      },
      {
        "number": "9",
        "name": "CLR",
        "type": "input",
        "description": "Falling-edge-sensitive asynchronous clear input that loads the CLR code register value (zero, midscale or full scale) into the DAC registers, with LDAC pulses ignored while low and defaulting to clearing the output to 0 V."
      },
      {
        "number": "10",
        "name": "VOUTH",
        "type": "output",
        "description": "Analog output voltage from DAC H with a rail-to-rail output amplifier."
      },
      {
        "number": "11",
        "name": "VOUTF",
        "type": "output",
        "description": "Analog output voltage from DAC F with a rail-to-rail output amplifier."
      },
      {
        "number": "12",
        "name": "VOUTD",
        "type": "output",
        "description": "Analog output voltage from DAC D with a rail-to-rail output amplifier."
      },
      {
        "number": "13",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B with a rail-to-rail output amplifier."
      },
      {
        "number": "14",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "15",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to a 32-bit shift register, with data clocked in on the falling edge of the serial clock."
      },
      {
        "number": "16",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input that clocks data into the input shift register on its falling edge at rates of up to 50 MHz."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 10,
        "cost_usd": 0.023,
        "at": "2026-11-02T16:54:37"
      },
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        "pages": 30,
        "sha256": "aa0519e5e63a0198",
        "source_tier": "mfr"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "footprint_binding": "identity",
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        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
        "file": "ad5668bruz-2reel7-etched.step",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "sha256": "0931349f51584522e0770cf886adc24a5764cd9690500f1ad096c200d9d2417a",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "ADI(亚德诺)",
      "Package": "TSSOP-16",
      "Category": "",
      "Pins": "16"
    },
    "characteristics": {
      "version": 1,
      "source": "datasheet",
      "datasheet_sha256": "aa0519e5e63a01986cf16ae4ac9765189c1c3ef5d900eb3686842da78162019b",
      "rows": [
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          "name": "Relative Accuracy",
          "symbol": "",
          "kind": "tolerance",
          "unit": "LSB",
          "min": -16,
          "typ": 8,
          "max": 16,
          "conditions": "See Figure 7",
          "source_page": 4,
          "source": "datasheet"
        },
        {
          "name": "Zero-Code Error",
          "symbol": "",
          "kind": "electrical",
          "unit": "mV",
          "min": null,
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          "max": 19,
          "conditions": "All 0s loaded to DAC register (see Figure 26)",
          "source_page": 4,
          "source": "datasheet"
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        {
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          "unit": "% FSR",
          "min": null,
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          "max": -1,
          "conditions": "All 1s loaded to DAC register (see Figure 27)",
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          "name": "Reference Output Voltage",
          "symbol": "",
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          "min": 2.495,
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          "max": 2.505,
          "conditions": "AD5668-2, AD5668-3; at ambient",
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          "name": "Reference Current",
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          "name": "Input Low Voltage",
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          "min": null,
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          "max": 0.8,
          "conditions": "VDD = 5 V",
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          "source": "datasheet"
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          "name": "Input High Voltage",
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          "min": 2,
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          "conditions": "VDD = 5 V",
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        {
          "name": "VDD",
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          "min": 4.5,
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          "conditions": "All digital inputs at 0 or VDD, DAC active, excludes load current",
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        {
          "name": "IDD (Normal Mode), internal reference off",
          "symbol": "IDD",
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          "conditions": "VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference off",
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        {
          "name": "IDD (Normal Mode), internal reference on",
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          "max": 2.25,
          "conditions": "VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference on",
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          "name": "IDD (All Power-Down Modes)",
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        {
          "name": "DC Power Supply Rejection Ratio",
          "symbol": "PSRR",
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          "max": null,
          "conditions": "VDD ± 10%",
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          "name": "DC Crosstalk (External Reference), full-scale output change",
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          "name": "DC Crosstalk (External Reference), load current change",
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        {
          "name": "DC Crosstalk (External Reference), powering down",
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          "name": "DC Crosstalk (Internal Reference), full-scale output change",
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          "name": "DC Crosstalk (Internal Reference), load current change",
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          "conditions": "Upper limit printed as VDD",
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          "name": "Capacitive Load Stability",
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          "name": "Capacitive Load Stability",
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          "name": "DC Output Impedance",
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          "name": "Short-Circuit Current",
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          "max": null,
          "conditions": "VDD = 5 V",
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          "name": "Power-Up Time",
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          "conditions": "Coming out of power-down mode, VDD = 5 V",
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          "name": "Output Voltage Settling Time",
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          "conditions": "¼ to ¾ scale settling to ±2 LSB (16-bit resolution)",
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        {
          "name": "VDD to GND",
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          "conditions": "Referenced to GND",
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        {
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