component

74HC30S

Public Made by Adom

by adom

GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentlogic74hc30s
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74hc30s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
74hc30s-etched.fit.json 74hc30s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc30s-etched.glb 74hc30s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc30s-etched.step 74hc30s: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc30s.glb Publish 0.1.0 · Ray 2mo ago
74hc30s.kicad_mod Publish 0.1.0 · Ray 2mo ago
74hc30s.kicad_sym Publish 0.1.0 · Ray 2mo ago
74hc30s.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray 2mo ago
74hc30s.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
page.json 74hc30s: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 27d ago
README.md 74hc30s: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HC30S

GR · Gates · SOP-14

74HC30S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input NAND gate input A. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
2 B input NAND gate input B. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
3 C input NAND gate input C. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
4 D input NAND gate input D. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
5 E input NAND gate input E. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
6 F input NAND gate input F. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
7 GND power_in Ground / 0 V reference for the device.
8 Y output 8-input NAND gate output Y = NOT(A·B·C·D·E·F·G·H). Buffered push-pull CMOS output; sources/sinks up to 4.0 mA at VCC=4.5 V and 5.2 mA at VCC=6.0 V. Absolute-max IOUT ±25 mA.
9 NC unconnected No connection. Leave floating or tie to a static level.
10 NC unconnected No connection. Leave floating or tie to a static level.
11 G input NAND gate input G. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
12 H input NAND gate input H. CMOS logic input; VIH ≥ 4.2 V and VIL ≤ 1.8 V at VCC = 6 V. Input current ≤ 1 µA.
13 NC unconnected No connection. Leave floating or tie to a static level.
14 VCC power_in Positive supply. Operating range 2.0 V to 6.0 V (typ 5 V); absolute-max 6.5 V. Bypass to GND with a local ceramic capacitor near the pin.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-14
Category Logic
Pins 14

Ordering variants

  • 74HC30SS
  • 74HC30SD

CAD (KiCad official)

  • Symbol: 74HC30S
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc30s-etched.step / 74hc30s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc30s.step / 74hc30s.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74hc30s.step 195 KB You want the bare part, or you mark your own boards.
74hc30s-etched.step 2.0 MB You want the part with 74HC30S already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 499 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (5 pp, sha256 53b21b6590ca178d, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF