USBLC6-2SC6
Public Unreviewedby adom
USBLC6-2SC6 with source-traceable pin map and explicitly nominal drawing-led CAD.
USBLC6-2SC6
STMicroelectronics · 6-pin SOT-23.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected data line 1 (e.g. USB D+ or D-). Bidirectional signal pin clamped by steering diodes to GND and VBUS; also tied to pin 6 (same net). Typical capacitance to GND 2.5 pF, max 3.5 pF at 1 MHz. |
| 2 | GND | power_in | Ground reference. Cathode return for the lower steering diodes and anode of the internal clamping Zener; must be connected to system ground with the shortest possible trace to minimize parasitic inductance during an ESD event. |
| 3 | I/O2 | passive | Protected data line 2 (e.g. USB D- or D+). Bidirectional signal pin clamped by steering diodes to GND and VBUS; also tied to pin 4 (same net). Typical capacitance to GND 2.5 pF, max 3.5 pF at 1 MHz. |
| 4 | I/O2 | passive | Second bond pad for the I/O2 data line; internally shorted to pin 3. Route the data line to either pin 3 or 4 (or both) as convenient for the PCB layout. |
| 5 | VBUS | power_in | Positive supply rail reference for the ESD clamp (typ +5 V for USB). Provides the upper rail for the steering diodes and is clamped to GND through the internal Zener; VBR = 6 V min at IF = 1 mA. Bypass to GND with a 100 nF capacitor placed close to the device for optimal ESD performance. |
| 6 | I/O1 | passive | Second bond pad for the I/O1 data line; internally shorted to pin 1. Route the data line to either pin 1 or 6 (or both) as convenient for the PCB layout. |
Model correction and provenance
Original Adom nominal model from the manufacturer package dimensions: 2.9 ×1.6 mm body,2.8 mm lead span,0.95 mm pitch and1.20 mm height. The previous generic1.55 mm model exceeded ST's1.45 mm maximum. This is drawing-led CAD, not a manufacturer STEP or a tolerance envelope. Mold taper, lead bends and materials are illustrative.
The marked variant adds a0.005 mm virtual full-MPN identification layer. It does not reproduce factory markings or physical etching. Board-use models omit the hero's nonphysical footprint/signal annotations.
The existing KiCad-derived symbol and footprint retain the library license exception. The footprint remains a generic variant; manufacturer land recommendations and process qualification require separate review.
See provenance, reference PDF, and manufacturer source. Reference review: Mirror older revision; dimensions independently checked against ST DS4260 Rev7 Dec2021 Table3 page12.
Local model review, native file validation, published wiki visual review and physical qualification are distinct.
# USBLC6-2SC6
STMicroelectronics · 6-pin SOT-23.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected data line 1 (e.g. USB D+ or D-). Bidirectional signal pin clamped by steering diodes to GND and VBUS; also tied to pin 6 (same net). Typical capacitance to GND 2.5 pF, max 3.5 pF at 1 MHz. |
| 2 | GND | power_in | Ground reference. Cathode return for the lower steering diodes and anode of the internal clamping Zener; must be connected to system ground with the shortest possible trace to minimize parasitic inductance during an ESD event. |
| 3 | I/O2 | passive | Protected data line 2 (e.g. USB D- or D+). Bidirectional signal pin clamped by steering diodes to GND and VBUS; also tied to pin 4 (same net). Typical capacitance to GND 2.5 pF, max 3.5 pF at 1 MHz. |
| 4 | I/O2 | passive | Second bond pad for the I/O2 data line; internally shorted to pin 3. Route the data line to either pin 3 or 4 (or both) as convenient for the PCB layout. |
| 5 | VBUS | power_in | Positive supply rail reference for the ESD clamp (typ +5 V for USB). Provides the upper rail for the steering diodes and is clamped to GND through the internal Zener; VBR = 6 V min at IF = 1 mA. Bypass to GND with a 100 nF capacitor placed close to the device for optimal ESD performance. |
| 6 | I/O1 | passive | Second bond pad for the I/O1 data line; internally shorted to pin 1. Route the data line to either pin 1 or 6 (or both) as convenient for the PCB layout. |
## Model correction and provenance
Original Adom nominal model from the manufacturer package dimensions: 2.9 ×1.6 mm body,2.8 mm lead span,0.95 mm pitch and1.20 mm height. The previous generic1.55 mm model exceeded ST's1.45 mm maximum. This is drawing-led CAD, not a manufacturer STEP or a tolerance envelope. Mold taper, lead bends and materials are illustrative.
The marked variant adds a0.005 mm virtual full-MPN identification layer. It does not reproduce factory markings or physical etching. Board-use models omit the hero's nonphysical footprint/signal annotations.
The existing KiCad-derived symbol and footprint retain the library license exception. The footprint remains a generic variant; manufacturer land recommendations and process qualification require separate review.
See [provenance](provenance-correction.json), [reference PDF](docs/manufacturer-reference.pdf), and [manufacturer source](https://www.st.com/resource/en/datasheet/usblc6-2.pdf). Reference review: Mirror older revision; dimensions independently checked against ST DS4260 Rev7 Dec2021 Table3 page12.
Local model review, native file validation, published wiki visual review and physical qualification are distinct.