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Contents

README

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ADS131M02IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-20

ADS131M02IPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Analog supply voltage (2.7V to 3.6V nominal in normal operating modes; 2.4V to 3.6V in standby/current-detect modes); connect a 1-µF capacitor to AGND.
2 AGND power_in Analog supply ground.
3 AIN0P input Positive analog input channel 0; differential input voltage range ±VREF/Gain (VREF = 1.2V) with absolute input AGND - 1.3V to AVDD (gain 1-4) or AGND - 1.3V to AVDD - 1.8V (gain 8-128).
4 AIN0N input Negative analog input channel 0; differential input voltage range ±VREF/Gain (VREF = 1.2V) with absolute input AGND - 1.3V to AVDD (gain 1-4) or AGND - 1.3V to AVDD - 1.8V (gain 8-128).
5 AIN1N input Negative analog input channel 1; differential input voltage range ±VREF/Gain (VREF = 1.2V) with absolute input AGND - 1.3V to AVDD (gain 1-4) or AGND - 1.3V to AVDD - 1.8V (gain 8-128).
6 AIN1P input Positive analog input channel 1; differential input voltage range ±VREF/Gain (VREF = 1.2V) with absolute input AGND - 1.3V to AVDD (gain 1-4) or AGND - 1.3V to AVDD - 1.8V (gain 8-128).
7 NC unconnected Not connected.
8 NC unconnected Not connected.
9 NC unconnected Not connected.
10 NC unconnected Not connected.
11 SYNC/RESET input Active-low digital input for synchronization (pulse duration 1-2047 tCLKIN) or system reset (pulse duration ≥2048 tCLKIN); enables alignment of conversions with external events or hardware reset.
12 CS input Active-low chip select digital input; device ignores all SPI communication and DOUT remains high impedance when CS is high.
13 DRDY output Active-low digital output indicating new ADC conversion data available in conversion mode or current-detect threshold conditions met in current-detect mode.
14 SCLK input Serial clock digital input (SPI mode CPOL=0, CPHA=1); output data transition on SCLK rising edge, input data latched on falling edge.
15 DOUT tri_state Serial data output (SPI MISO); shifts ADC conversion data and command responses on SCLK rising edges when CS is low; assumes high-impedance state when CS is high.
16 DIN input Serial data input (SPI MOSI); serial commands shifted in on SCLK falling edges when CS is low.
17 CLKIN input Master clock input (LVCMOS); required frequency 0.3-8.4 MHz (HR mode), 0.3-4.15 MHz (LP mode), or 0.3-2.08 MHz (VLP mode) with 40-60% duty cycle; modulator frequency fMOD = fCLKIN / 2.
18 CAP power_out Analog output from internal digital LDO regulator (nominally 1.8V); connect a 220-nF capacitor to DGND.
19 DGND power_in Digital supply ground.
20 DVDD power_in Digital I/O supply voltage (1.8V or 3.3V supported; 2.7V to 3.6V normal operating, 1.65V to 2.0V if CAP tied to DVDD); connect a 1-µF capacitor to DGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category Data Acquisition
Pins 20

CAD (KiCad official)

  • Symbol: ADS131M02IPWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ads131m02ipwr-etched.step / ads131m02ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads131m02ipwr.step / ads131m02ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (95 pp, sha256 6165dbb0c979f300, retrieved 2026-09-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF