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5P49V5901B000NLGI8

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by Ray

RENESAS Clock Generators, PLLs, Frequency Synthesizers, QFN-24(4x4). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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5P49V5901B000NLGI8

RENESAS · Clock Generators, PLLs, Frequency Synthesizers · QFN-24(4x4)

5P49V5901B000NLGI8 from RENESAS, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input Differential clock input (true). Accepts LVDS/LVPECL/HCSL differential clocks or single-ended reference from 1 MHz to 350 MHz. Weak internal 100 kΩ pull-down.
2 CLKINB input Complementary differential clock input (inverting half of CLKIN pair). Weak internal 100 kΩ pull-down.
3 XOUT output Crystal oscillator interface output. Connect to the far side of an 8-40 MHz fundamental-mode quartz crystal (paired with XIN/REF); leave floating if the crystal oscillator is not used.
4 XIN/REF input Crystal oscillator input, or single-ended LVCMOS reference clock input (1-200 MHz). When overdriven as REF, keep input voltage ≤ 1.2 V max (see 'Overdriving the XIN/REF Interface').
5 VDDA power_in Analog PLL power supply. 1.8 V, 2.5 V, or 3.3 V; must be the same voltage as VDDD.
6 CLKSEL input Input reference select in manual switchover mode. 0 = XIN/REF+XOUT (default); 1 = CLKIN/CLKINB. Polarity is reprogrammable via I2C (see Table 4). Weak internal pull-down.
7 SD/OE input Dual-function shutdown / output-enable. SH bit selects mode; SP bit sets OE polarity (default active-LOW). In SD, chip shuts down (differential outputs driven high/low, LVCMOS outputs driven low); in OE, disabled outputs can be tri-stated or driven per programming. Weak internal pull-down.
8 SEL1/SDA bidirectional Configuration select bit 1, or I2C SDA data line. Function is chosen at power-up by the OUT0_SEL_I2CB latched pin. Weak internal pull-down.
9 SEL0/SCL bidirectional Configuration select bit 0, or I2C SCL clock line. Function is chosen at power-up by the OUT0_SEL_I2CB latched pin. Weak internal pull-down.
10 VDDO4 power_in Output-bank 4 power supply. 1.8-3.3 V; sets the output voltage/standard for OUT4/OUT4B.
11 OUT4 output Clock output 4 (true). Configurable as one differential pair with OUT4B (LVPECL/LVDS/HCSL) or as one of two independent LVCMOS outputs.
12 OUT4B output Complementary clock output 4 (inverting/second half of OUT4 pair).
13 OUT3B output Complementary clock output 3 (inverting/second half of OUT3 pair).
14 OUT3 output Clock output 3 (true). Configurable as one differential pair with OUT3B or as two independent LVCMOS outputs.
15 VDDO3 power_in Output-bank 3 power supply. 1.8-3.3 V; sets the output voltage/standard for OUT3/OUT3B.
16 OUT2B output Complementary clock output 2 (inverting/second half of OUT2 pair).
17 OUT2 output Clock output 2 (true). Configurable as one differential pair with OUT2B or as two independent LVCMOS outputs.
18 VDDO2 power_in Output-bank 2 power supply. 1.8-3.3 V; sets the output voltage/standard for OUT2/OUT2B.
19 OUT1B output Complementary clock output 1 (inverting/second half of OUT1 pair).
20 OUT1 output Clock output 1 (true). Configurable as one differential pair with OUT1B or as two independent LVCMOS outputs.
21 VDDO1 power_in Output-bank 1 power supply. 1.8-3.3 V; sets the output voltage/standard for OUT1/OUT1B.
22 VDDD power_in Digital core power supply. 1.8 V, 2.5 V, or 3.3 V; must be the same voltage as VDDA.
23 VDDO0 power_in Power supply for the OUT0_SEL_I2CB LVCMOS reference output driver. 1.8-3.3 V; sets output voltage level for OUT0.
24 OUT0_SEL_I2CB bidirectional Latched-input / LVCMOS-output triple-function pin. At power-up, the pin is sampled: a weak 10 kΩ pull-up configures pins 8/9 as SEL1/SEL0 (hardware config select); a weak 10 kΩ pull-down or floating configures pins 8/9 as I2C SDA/SCL. After power-up, the pin drives an LVCMOS reference clock output (OUT0).
EPAD GND power_in Exposed thermal/ground pad on the package underside. Must be connected to the PCB ground plane for both electrical ground and thermal dissipation.

Key specifications

Parameter Value
Manufacturer RENESAS
Package QFN-24(4x4)
Category Clock/Timing
Pins 25

Ordering variants

Same part, different packaging or reel option.

  • 5P49V5901B000NLGI8

CAD (KiCad official)

  • Symbol: 5P49V5901B000NLGI8
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (None pp, sha256 220fbf224fae5a9c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF