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Contents

README

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MSP430F413IPMR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

MSP430F413IPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DVCC power_in Digital supply voltage, positive terminal supplying all parts except those supplied via AVCC.
2 P6.3 bidirectional General-purpose digital I/O.
3 P6.4 bidirectional General-purpose digital I/O.
4 P6.5 bidirectional General-purpose digital I/O.
5 P6.6 bidirectional General-purpose digital I/O.
6 P6.7 bidirectional General-purpose digital I/O.
7 NC unconnected Not internally connected; connection to VSS recommended.
8 XIN input Input port for crystal oscillator XT1; standard or watch crystals can be connected.
9 XOUT output Output terminal of crystal oscillator XT1.
10 NC unconnected Not internally connected; connection to VSS recommended.
11 NC unconnected Not internally connected; connection to VSS recommended.
12 P5.1/S0 bidirectional General-purpose digital I/O or LCD segment output 0 when LCD mode enabled.
13 P5.0/S1 bidirectional General-purpose digital I/O or LCD segment output 1 when LCD mode enabled.
14 P4.7/S2 bidirectional General-purpose digital I/O or LCD segment output 2 when LCD mode enabled.
15 P4.6/S3 bidirectional General-purpose digital I/O or LCD segment output 3 when LCD mode enabled.
16 P4.5/S4 bidirectional General-purpose digital I/O or LCD segment output 4 when LCD mode enabled.
17 P4.4/S5 bidirectional General-purpose digital I/O or LCD segment output 5 when LCD mode enabled.
18 P4.3/S6 bidirectional General-purpose digital I/O or LCD segment output 6 when LCD mode enabled.
19 P4.2/S7 bidirectional General-purpose digital I/O or LCD segment output 7 when LCD mode enabled.
20 P4.1/S8 bidirectional General-purpose digital I/O or LCD segment output 8 when LCD mode enabled.
21 P4.0/S9 bidirectional General-purpose digital I/O or LCD segment output 9 when LCD mode enabled.
22 P3.7/S10 bidirectional General-purpose digital I/O or LCD segment output 10 when LCD mode enabled.
23 P3.6/S11 bidirectional General-purpose digital I/O or LCD segment output 11 when LCD mode enabled.
24 P3.5/S12 bidirectional General-purpose digital I/O or LCD segment output 12 when LCD mode enabled.
25 P3.4/S13 bidirectional General-purpose digital I/O or LCD segment output 13 when LCD mode enabled.
26 P3.3/S14 bidirectional General-purpose digital I/O or LCD segment output 14 when LCD mode enabled.
27 P3.2/S15 bidirectional General-purpose digital I/O or LCD segment output 15 when LCD mode enabled.
28 P3.1/S16 bidirectional General-purpose digital I/O or LCD segment output 16 when LCD mode enabled.
29 P3.0/S17 bidirectional General-purpose digital I/O or LCD segment output 17 when LCD mode enabled.
30 P2.7/S18 bidirectional General-purpose digital I/O or LCD segment output 18 when LCD mode enabled.
31 P2.6/CAOUT/S19 bidirectional General-purpose digital I/O or comparator_A output or LCD segment output 19 when LCD mode enabled.
32 P2.5/S20 bidirectional General-purpose digital I/O or LCD segment output 20 when LCD mode enabled.
33 P2.4/S21 bidirectional General-purpose digital I/O or LCD segment output 21 when LCD mode enabled.
34 P2.3/S22 bidirectional General-purpose digital I/O or LCD segment output 22 when LCD mode enabled.
35 P2.2/S23 bidirectional General-purpose digital I/O or LCD segment output 23 when LCD mode enabled.
36 COM0 output Common output for LCD backplanes COM0-3.
37 P5.2/COM1 bidirectional General-purpose digital I/O or common output for LCD backplanes COM0-3.
38 P5.3/COM2 bidirectional General-purpose digital I/O or common output for LCD backplanes COM0-3.
39 P5.4/COM3 bidirectional General-purpose digital I/O or common output for LCD backplanes COM0-3.
40 R03 input Input port for fourth positive (lowest) analog LCD level (V5).
41 P5.5/R13 bidirectional General-purpose digital I/O or input port for third most positive analog LCD level (V4 or V3).
42 P5.6/R23 bidirectional General-purpose digital I/O or input port for second most positive analog LCD level (V2).
43 P5.7/R33 bidirectional General-purpose digital I/O or output port for most positive analog LCD level (V1).
44 P2.1 bidirectional General-purpose digital I/O.
45 P2.0/TA2 bidirectional General-purpose digital I/O or Timer_A capture input (CCI2A) or compare output (Out2).
46 P1.7/CA1 bidirectional General-purpose digital I/O or comparator_A input.
47 P1.6/CA0 bidirectional General-purpose digital I/O or comparator_A input.
48 P1.5/TACLK/ACLK bidirectional General-purpose digital I/O or Timer_A clock input or ACLK output.
49 P1.4 bidirectional General-purpose digital I/O.
50 P1.3/SVSOUT bidirectional General-purpose digital I/O or SVS comparator output.
51 P1.2/TA1 bidirectional General-purpose digital I/O or Timer_A capture input (CCI1A) or compare output (Out1).
52 P1.1/TA0/MCLK bidirectional General-purpose digital I/O or Timer_A capture input (CCI0B) or MCLK output; TA0 is input only on this pin.
53 P1.0/TA0 bidirectional General-purpose digital I/O or Timer_A capture input (CCI0A) or compare output (Out0).
54 TDO/TDI bidirectional Test data output or programming data input terminal.
55 TDI/TCLK input Test data input or test clock input; device protection fuse connected to TDI.
56 TMS input Test mode select input for device programming and test.
57 TCK input Test clock input for device programming and test.
58 RST/NMI input Reset input or nonmaskable interrupt input.
59 P6.0 bidirectional General-purpose digital I/O.
60 P6.1 bidirectional General-purpose digital I/O.
61 P6.2 bidirectional General-purpose digital I/O.
62 AVSS power_in Negative terminal supplying SVS, brownout, oscillator, and comparator_A; must be externally connected to DVSS.
63 DVSS power_in Digital supply voltage, negative terminal supplying all digital parts except those supplied via AVCC/AVSS.
64 AVCC power_in Positive terminal supplying SVS, brownout, oscillator, comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior to DVCC.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

CAD (KiCad official)

  • Symbol: MSP430F413IPMR
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: msp430f413ipmr-etched.step / msp430f413ipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430f413ipmr.step / msp430f413ipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (66 pp, sha256 221c0acc6935c96a, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF