UCC27201AQDDARQ1 from Texas Instruments, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Positive supply to the lower gate driver, to be decoupled to VSS (GND) with a typical capacitor range of 0.22μF to 1.0μF.
2	HB	power_in	High-side bootstrap supply, with an on-chip bootstrap diode and an external bootstrap capacitor whose typical HB bypass range is 0.022μF to 0.1μF, dependent on the high-side MOSFET gate charge.
3	HO	output	High-side gate driver output, connected to the gate of the high-side power MOSFET.
4	HS	power_in	High-side source connection, tied to the high-side MOSFET source and the negative side of the bootstrap capacitor, with an absolute maximum of -18V for repetitive pulses under 100 ns.
5	HI	input	High-side input that controls the HO output, with TTL-compatible thresholds.
6	LI	input	Low-side input that controls the LO output, with TTL-compatible thresholds.
7	VSS	power_in	Negative supply terminal for the device, which is generally grounded.
8	LO	output	Low-side gate driver output, connected to the gate of the low-side power MOSFET.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SO-8
Category	Motor Driver ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD supply voltage	VDD	-0.3		20	V		4
Input voltages on HI and LI	VHI, VLI	-0.3		20	V		4
Voltage on HS DC	VHS	-1		120	V	DC	4
Voltage on HS repetitive pulse	VHS	-18		120	V	Repetitive pulse < 100 ns	4
Voltage on HB	VHB	-0.3		120	V		4
Voltage on HB-HS	VHB-VHS	-0.3		20	V		4
Output voltage on LO	VLO	-2			V	Repetitive pulse < 100 ns; printed upper limit VDD + 0.3 V	4
Operating junction temperature	TJ	-40		150	°C		4
Storage temperature	Tstg	-65		150	°C		4
VDD supply voltage	VDD	8	12	17	V		4
Voltage on HS	VHS	-1		105	V		4
Voltage on HS repetitive pulse	VHS	-15		110	V	Repetitive pulse < 100 ns	4
Operating junction temperature	TJ	-40		150	°C		4
VDD quiescent current	IDD		0.11	0.8	mA	VLI = VHI = 0 V	5
VDD operating current	IDDO		1	3	mA	f = 500 kHz, CLOAD = 0	5
Boot voltage quiescent current	IHB		0.065	0.8	mA	VLI = VHI = 0 V	5
Boot voltage operating current	IHBO		0.9	3	mA	f = 500 kHz, CLOAD = 0	5
HB to VSS quiescent current	IHBS		0.0005	1	μA	VHS = VHB = 105 V	5
Input voltage high threshold	VHIT	1.9	2.3	2.7	V		5
Input voltage low threshold	VLIT	1.3	1.6	1.9	V		5
Input pulldown resistance	RIN		68		kΩ	VIN = 3V	5
VDD rising threshold	VDDR	6.2	7.1	7.8	V		5
VHB rising threshold	VHBR	5.8	6.7	7.2	V		5
Low-current forward voltage	VF		0.65	0.85	V	IVDD - HB = 100 μA	5
High-current forward voltage	VFI		0.85	1.1	V	IVDD - HB = 100 mA	5
Dynamic resistance, ΔVF/ΔI	RD		0.65	1	Ω	IVDD - HB = 120 mA and 100 mA	5
LO low level output voltage	VLOL		0.1	0.4	V	ILO = 100 mA	5
LO high level output voltage	VLOH		0.13	0.42	V	ILO = -100 mA, VLOH = VDD, VLO	5
HO low level output voltage	VHOL		0.1	0.4	V	IHO = 100 mA	5
HO high level output voltage	VHOH		0.13	0.42	V	IHO = -100 mA, VHOH = VHB- VHO	5
LO propagation delay, VLI falling to VLO falling	tDLFF		22	50	ns	CLOAD = 0 pF, from VLIT of LI to 90% of LO falling	5
HO propagation delay, VHI falling to VHO falling	tDHFF		22	50	ns	CLOAD = 0 pF, from VIT of HI to 90% of HO falling	6
LO propagation delay, VLI rising to VLO rising	tDLRR		22	50	ns	CLOAD = 0 pF, from VHIT of LI to 10% of LO rising	6
HO propagation delay, VHI rising to VHO rising	tDHRR		22	50	ns	CLOAD = 0 pF, from VHIT of HI to 10% of HO rising	6
Delay matching, LI ON, HI OFF	tMON		1	7	ns		6
Delay matching, LI OFF, HI ON	tMOFF		1	7	ns		6
LO rise time (3 V to 9 V)	tR_LO_p1		0.26	0.6	μs	CLOAD = 0.1 μF, (3V to 9V)	6
HO rise time (3 V to 9 V)	tR_HO_p1		0.26	0.6	μs	CLOAD = 0.1 μF, (3V to 9V)	6
LO fall time (9 V to 3 V)	tF_LO_p1		0.22	0.6	μs	CLOAD = 0.1 μF, (9V to 3V)	6
HO fall time (9 V to 3 V)	tF_HO_p1		0.22	0.6	μs	CLOAD = 0.1 μF, (9V to 3V)	6
Junction-to-ambient thermal resistance	RθJA		44.8		°C/W		4
Junction-to-case (top) thermal resistance	RθJC(top)		68.5		°C/W		4
Junction-to-board thermal resistance	RθJB		20		°C/W		4
Junction-to-top characterization parameter	ψJT		6.9		°C/W		4
Junction-to-board characterization parameter	ψJB		20		°C/W		4
Junction-to-case (bottom) thermal resistance	RθJC(bot)		8.4		°C/W		5

CAD (KiCad official)

Symbol: UCC27201AQDDARQ1
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SO-8 (KiCad packages3D, STEP)
3D model files: ucc27201aqddarq1-etched.step / ucc27201aqddarq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ucc27201aqddarq1.step / ucc27201aqddarq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (33 pp, sha256 b909b640963f85b2, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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UCC27201AQDDARQ1

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