component
TPS53126RGET
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTPS53126RGET
Texas Instruments · DC-DC Controllers · VQFN-24(4x4)
TPS53126RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VO1 | input | Output voltage input for channel 1 on-time adjustment and output discharge, connected directly to the VO1 output voltage. |
| 2 | VFB1 | input | Channel 1 D-CAP2 feedback input, connected to the output voltage through a resistor divider. |
| 3 | GND | power_in | Signal ground, to be connected to PGND1, PGND2 and the system ground at a single point. |
| 4 | TEST1 | output | Test interface pin not used in application, to be connected directly to GND. |
| 5 | VFB2 | input | Channel 2 D-CAP2 feedback input, connected to the output voltage through a resistor divider. |
| 6 | VO2 | input | Output voltage input for channel 2 on-time adjustment and output discharge, connected directly to the VO2 output voltage. |
| 7 | EN2 | input | Channel 2 high-level enable pin; EN1 and EN2 are rated -0.1 V to 24 V in recommended operating conditions. |
| 8 | VBST2 | power_in | Boost supply input for the channel 2 high-side NFET driver, bypassed to SW2 with a high-quality 0.1 µF ceramic capacitor (external Schottky optional if forward drop is critical); VBST1/VBST2 are rated up to 5.5 V with respect to SWx. |
| 9 | DRVH2 | output | Channel 2 high-side MOSFET gate driver output, switching between SW2 (OFF) and VBST2 (ON). |
| 10 | SW2 | bidirectional | Channel 2 switch node for the high-side driver and current comparator; rated -1.8 V to 24 V in recommended operating conditions. |
| 11 | DRVL2 | output | Channel 2 low-side MOSFET gate driver output, PGND2-referenced, switching between PGND2 (OFF) and VREG5 (ON). |
| 12 | PGND2 | power_in | Channel 2 power ground for the low-side driver and current comparator, to be connected strongly to PGND1 and GND near the IC. |
| 13 | TRIP2 | input | Channel 2 over-current trip programming pin, connected to GND through a resistor to set the low-side RDS(on) current-limit threshold (TRIP1/TRIP2 rated -0.1 V to 0.3 V). |
| 14 | TEST2 | input | Frequency select pin: connect to GND for 350 kHz switching or to V5FILT for 700 kHz switching. |
| 15 | V5FILT | power_in | 5 V supply input for the control circuit (excluding MOSFET drivers), bypassed to GND with a minimum 1.0 µF high-quality ceramic capacitor; rated 4.5 V to 5.5 V and connected to VREG5 through an internal 10 Ω resistor. |
| 16 | VREG5 | power_out | Output of the 5 V linear regulator and supply for the MOSFET drivers, bypassed to GND with a minimum 4.7 µF high-quality ceramic capacitor; connected to V5FILT through an internal 10 Ω resistor. |
| 17 | VIN | power_in | Supply input for the 5 V linear regulator, operating from 4.5 V to 24 V. |
| 18 | TRIP1 | input | Channel 1 over-current trip programming pin, connected to GND through a resistor to set the low-side RDS(on) current-limit threshold. |
| 19 | PGND1 | power_in | Channel 1 power ground for the low-side driver and current comparator, to be connected strongly to PGND2 and GND near the IC. |
| 20 | DRVL1 | output | Channel 1 low-side MOSFET gate driver output, PGND1-referenced, switching between PGND1 (OFF) and VREG5 (ON). |
| 21 | SW1 | bidirectional | Channel 1 switch node for the high-side driver and current comparator; rated -1.8 V to 24 V in recommended operating conditions. |
| 22 | DRVH1 | output | Channel 1 high-side MOSFET gate driver output, switching between SW1 (OFF) and VBST1 (ON). |
| 23 | VBST1 | power_in | Boost supply input for the channel 1 high-side NFET driver, bypassed to SW1 with a high-quality 0.1 µF ceramic capacitor (external Schottky optional if forward drop is critical); VBST1/VBST2 are rated up to 5.5 V with respect to SWx. |
| 24 | EN1 | input | Channel 1 high-level enable pin; EN1 and EN2 are rated -0.1 V to 24 V in recommended operating conditions. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Power Management ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply input voltage range | VIN | 4.5 | 24 | V | 4 | ||
| V5FILT input voltage range | V5FILT | 4.5 | 5.5 | V | 4 | ||
| VBST1, VBST2 voltage range | VBST1, VBST2 | -0.1 | 30 | V | 4 | ||
| VBST1, VBST2 voltage range (wrt SWx) | VBST1, VBST2 (wrt SWx) | -0.1 | 5.5 | V | 4 | ||
| VFB1, VFB2, VO1, VO2, TEST1, TEST2 input voltage range | VFB1, VFB2, VO1, VO2, TEST1, TEST2 | -0.1 | 5.5 | V | 4 | ||
| TRIP1, TRIP2 input voltage range | TRIP1, TRIP2 | -0.1 | 0.3 | V | 4 | ||
| EN1, EN2 input voltage range | EN1, EN2 | -0.1 | 24 | V | 4 | ||
| SW1, SW2 input voltage range | SW1, SW2 | -1.8 | 24 | V | 4 | ||
| DRVH1, DRVH2 output voltage range | DRVH1, DRVH2 | -0.1 | 30 | V | 4 | ||
| DRVL1, DRVL2, VREG5 output voltage range | DRVL1, DRVL2, VREG5 | -0.1 | 5.5 | V | 4 | ||
| PGND1, PGND2 voltage range | PGND1, PGND2 | -0.1 | 0.1 | V | 4 | ||
| Operating free-air temperature (recommended) | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 4 | ||
| VIN, EN1, EN2 input voltage (absolute maximum) | VIN, EN1, EN2 | -0.3 | 26 | V | 4 | ||
| VBST1, VBST2 input voltage (absolute maximum) | VBST1, VBST2 | -0.3 | 32 | V | 4 | ||
| VBST1, VBST2 (wrt SWx) (absolute maximum) | VBST1, VBST2 (wrt SWx) | -0.3 | 6 | V | 4 | ||
| V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1, TEST2 input voltage (absolute maximum) | V5FILT, VFB1, VFB2, TRIP1, TRIP2, VO1, VO2, TEST1, TEST2 | -0.3 | 6 | V | 4 | ||
| SW1, SW2 voltage (absolute maximum) | SW1, SW2 | -2 | 26 | V | 4 | ||
| DRVH1, DRVH2 output voltage (absolute maximum) | DRVH1, DRVH2 | -1 | 32 | V | 4 | ||
| DRVH1, DRVH2 (wrt SWx) output voltage (absolute maximum) | DRVH1, DRVH2 (wrt SWx) | -0.3 | 6 | V | 4 | ||
| DRVL1, DRVL2, VREG5 output voltage (absolute maximum) | DRVL1, DRVL2, VREG5 | -0.3 | 6 | V | 4 | ||
| PGND1, PGND2 voltage (absolute maximum) | PGND1, PGND2 | -0.3 | 0.3 | V | 4 | ||
| Operating ambient temperature range (absolute maximum) | TA | -40 | 85 | °C | 4 | ||
| Junction temperature range (absolute maximum) | TJ | -40 | 150 | °C | 4 | ||
| VIN shutdown current... VIN supply current | IIN | 450 | 800 | μA | TA = 25°C, VREG5 tied to V5FLT, EN1 = EN2 = 5V, VFB1 = VFB2 = 0.8V, SW1 = SW2 = 0.5V | 5 | |
| VIN shutdown current | IVINSDN | 30 | 60 | μA | TA = 25°C, No load, EN1 = EN2 = 0 V, VREG5 = ON | 5 | |
| Bandgap initial regulation accuracy | VBG | -1 | 1 | % | TA = 25°C | 5 | |
| VFBx threshold voltage (TEST2 = 0 V) | VVFBTHLx | 755 | 765 | 775 | mV | TA = 25°C, TEST2 = 0 V, SWinj = OFF | 5 |
| VFBx threshold voltage (TEST2 = 0 V) | VVFBTHLx | 752 | 778 | mV | TA = -40°C to 85°C, TEST2 = 0 V, SWinj = OFF | 5 | |
| VFBx threshold voltage (TEST2 = V5FILT) | VVFBTHHx | 748 | 758 | 768 | mV | TA = 25°C, TEST2 = V5FILT, SWinj = OFF | 5 |
| VFBx threshold voltage (TEST2 = V5FILT) | VVFBTHHx | 745 | 771 | mV | TA = -40°C to 85°C, TEST2 = V5FILT, SWinj = OFF | 5 | |
| VFB input current | IVFB | -0.1 | -0.01 | 0.1 | μA | VFBx = 0.8 V, TA = 25°C | 5 |
| VO discharge resistance | RDischg | 40 | 80 | Ω | ENx = 0 V, VOx = 0.5 V, TA = 25°C | 5 | |
| VREG5 output voltage | VVREG5 | 4.6 | 5 | 5.2 | V | TA = 25°C, 5.5 V < VIN < 24 V, 0 < IVREG5 < 10 mA | 5 |
| DRVH resistance, source | RDRVH | 5.5 | 11 | Ω | Source, IDRVHx = -100 mA | 5 | |
| DRVH resistance, sink | RDRVH | 2.5 | 5 | Ω | Sink, IDRVHx = 100 mA | 5 | |
| DRVL resistance, source | RDRVL | 4 | 12 | Ω | Source, IDRVLx = -100 mA | 5 | |
| DRVL resistance, sink | RDRVL | 2 | 4 | Ω | Sink, IDRVLx = 100 mA | 5 | |
| Internal boot diode forward voltage | VFBST | 0.7 | 0.8 | 0.9 | V | VVREG5-VBSTx, IF = 10 mA, TA = 25°C | 5 |
| VBST leakage current | IVBSTLK | 0.1 | 1 | μA | VBSTx = 29 V, SWx = 24 V, TA = 25°C | 5 | |
| Internal soft start time | Tss | 0.85 | 1.2 | 1.4 | ms | Internal soft start VFBx = 0.735 V | 5 |
| V5FILT UVLO threshold, wake up | VUV5VFILT | 3.7 | 4 | 4.3 | V | Wake up | 5 |
| V5FILT UVLO threshold, hysteresis | VUV5VFILT | 0.2 | 0.3 | 0.4 | V | Hysteresis | 5 |
| ENx H-level input voltage | VENH | 2 | V | 6 | |||
| ENx L-level input voltage | VENL | 0.3 | V | 6 | |||
| TRIP source current | ITRIP | 8.5 | 10 | 11.5 | μA | VTRIPx = 0.1 V, TA = 25°C | 6 |
| OCP compensation offset | VOCLoff | -15 | 0 | 15 | mV | VTRIPx-GND = 60 mV, TA = 25°C | 6 |
| OCP compensation offset | VOCLoff | -20 | 20 | mV | VTRIPx-GND = 60 mV | 6 | |
| Current limit threshold setting range, VTRIPx-GND voltage | VRtrip | 30 | 300 | mV | 6 | ||
| Output OVP trip threshold, OVP detect | VOVP | 110 | 115 | 120 | % | OVP detect | 6 |
| Output UVP trip threshold, UVP detect | VUVP | 65 | 70 | 75 | % | UVP detect | 6 |
| Dead time, DRVHx-low to DRVLx-on | tD | 20 | 50 | 80 | ns | DRVHx-low to DRVLx-on | 6 |
| Dead time, DRVLx-low to DRVHx-on | tD | 20 | 40 | 80 | ns | DRVLx-low to DRVHx-on | 6 |
| Output UVP delay time | tUVPDEL | 17 | 30 | 40 | μs | 6 | |
| Output UVP enable delay time | tUVPEN | 1.2 | 2 | 2.5 | ms | UVP enable delay | 6 |
| Junction-to-ambient thermal resistance (RGE) | RθJA | 35.4 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (RGE) | RθJC(top) | 39.1 | °C/W | 5 | |||
| Junction-to-board thermal resistance (RGE) | RθJB | 13.6 | °C/W | 5 | |||
| Junction-to-top characterization parameter (RGE) | ψJT | 0.5 | °C/W | 5 | |||
| Junction-to-board characterization parameter (RGE) | ψJB | 13.6 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS53126RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps53126rget-etched.step/tps53126rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps53126rget.step/tps53126rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
5312495eb8164c7c, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).