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Contents

README

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74LCX573FT

TOSHIBA · Latches · TSSOP-20

74LCX573FT from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable; when HIGH all Q outputs are forced to high-impedance state; 5-V tolerant, VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
2 D0 input Data input bit 0; 5-V tolerant; latched to Q0 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
3 D1 input Data input bit 1; 5-V tolerant; latched to Q1 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
4 D2 input Data input bit 2; 5-V tolerant; latched to Q2 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
5 D3 input Data input bit 3; 5-V tolerant; latched to Q3 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
6 D4 input Data input bit 4; 5-V tolerant; latched to Q4 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
7 D5 input Data input bit 5; 5-V tolerant; latched to Q5 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
8 D6 input Data input bit 6; 5-V tolerant; latched to Q6 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
9 D7 input Data input bit 7; 5-V tolerant; latched to Q7 on falling edge of LE; VIH(min) = VCC×0.9 (VCC = 1.65-2.3 V).
10 GND power_in Ground reference; VCC/GND absolute maximum current ±100 mA.
11 LE input Latch enable; Q outputs track D inputs while HIGH, latch data on falling edge; minimum HIGH pulse width tw(H) = 3.3 ns (VCC = 3.3 V).
12 Q7 tri_state 3-state latch output bit 7; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
13 Q6 tri_state 3-state latch output bit 6; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
14 Q5 tri_state 3-state latch output bit 5; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
15 Q4 tri_state 3-state latch output bit 4; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
16 Q3 tri_state 3-state latch output bit 3; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
17 Q2 tri_state 3-state latch output bit 2; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
18 Q1 tri_state 3-state latch output bit 1; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
19 Q0 tri_state 3-state latch output bit 0; IOH = −24 mA min, IOL = 24 mA min (VCC = 3.0-3.6 V); high-impedance when OE is HIGH; 5-V tolerant.
20 VCC power_in Positive supply voltage; operating range 1.65 to 3.6 V; absolute maximum 6.5 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package TSSOP-20
Category Logic
Pins 20

CAD (KiCad official)

  • Symbol: 74LCX573FT
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74lcx573ft-etched.step / 74lcx573ft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74lcx573ft.step / 74lcx573ft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (10 pp, sha256 6ae4872c9b7d0076, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-4-6 (text+vision), consensus claude-opus-4-7 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF