component
UCC3895DWTR
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC3895DWTR
Texas Instruments · AC-DC Controllers And Regulators · SOIC-20-300mil
UCC3895DWTR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EAN | input | Inverting input to the error amplifier; keep voltage below 3.6 V for proper operation. |
| 2 | EAOUT | output | Error amplifier output; internally connected to non-inverting input of PWM comparator and no-load comparator; internally clamped to soft-start voltage. |
| 3 | RAMP | input | Inverting input of the PWM comparator; receives CT waveform in voltage/average current-mode control or current signal with slope compensation in peak current-mode control. |
| 4 | REF | power_out | 5-V ±1.2% precision voltage reference output supplying up to 5 mA; bypass with 0.1-μF low-ESR low-ESL capacitor to GND; do not use more than 4.7 μF total capacitance. |
| 5 | GND | power_in | Analog ground for all internal circuits except output stages. |
| 6 | SYNC | bidirectional | Bidirectional oscillator synchronization pin; functions as clock output when used as output or overrides internal oscillator when used as input with threshold 2.05-2.4 V; can be pulled to GND with 3.9 kΩ minimum. |
| 7 | CT | input | Oscillator timing capacitor; oscillator charges CT via programmed current generating sawtooth waveform with peak 2.35 V; supports 100-880 pF range. |
| 8 | RT | input | Oscillator timing resistor for programming switching frequency; valid range 40-120 kΩ with voltage maintained at 2.9-3.1 V nominal. |
| 9 | DELAB | input | Delay-programming pin for dead time between OUTA and OUTB complementary outputs; external resistor sets delay per formula tDELAY = 25 ns + (25×10⁻¹² × R_DEL / V_DEL). |
| 10 | DELCD | input | Delay-programming pin for dead time between OUTC and OUTD complementary outputs; external resistor sets delay per formula tDELAY = 25 ns + (25×10⁻¹² × R_DEL / V_DEL). |
| 11 | ADS | input | Adaptive delay-set pin; sets ratio between maximum and minimum programmed output delay dead time; must be 0-2.5 V and ≤ CS voltage for proper operation. |
| 12 | CS | input | Current sense input for cycle-by-cycle current limiting and overcurrent protection; peak current threshold 1.9-2.1 V, overcurrent threshold 2.4-2.6 V; delay to output 75-110 ns. |
| 13 | OUTD | output | 100-mA complementary MOS driver output; phase-shifted relative to OUTB; optimized to drive MOSFET gate driver circuits or transformers; high-level 250-400 mV, low-level 150-250 mV at 10 mA. |
| 14 | OUTC | output | 100-mA complementary MOS driver output; phase-shifted relative to OUTA; optimized to drive MOSFET gate driver circuits or transformers; high-level 250-400 mV, low-level 150-250 mV at 10 mA. |
| 15 | VDD | power_in | Power supply input pin; operating range 10-16.5 V; bypass with minimum 1-μF low-ESR low-ESL capacitor to PGND; additional 10-μF capacitor between VDD and PGND recommended. |
| 16 | PGND | power_in | Output stage ground providing ground reference for high-current output drivers; must be electrically tied to GND with low-impedance connection. |
| 17 | OUTB | output | 100-mA complementary MOS driver output; fully complementary to OUTA operating at ≈50% duty cycle and one-half oscillator frequency; high-level 250-400 mV, low-level 150-250 mV at 10 mA. |
| 18 | OUTA | output | 100-mA complementary MOS driver output; drives one half-bridge circuit in external power stage; operating at ≈50% duty cycle and one-half oscillator frequency; high-level 250-400 mV, low-level 150-250 mV at 10 mA. |
| 19 | SS/DISB | input | Soft-start and disable pin combining two independent functions; sources current ~35 μA during soft-start mode and sinks ~350 μA during soft-stop (overcurrent) mode; threshold 0.44-0.56 V. |
| 20 | EAP | input | Non-inverting input to the error amplifier; keep voltage below 3.6 V for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-20-300mil |
| Category | Power Management (PMIC) |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
UCC3895DWTR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
ucc3895dwtr-etched.step/ucc3895dwtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc3895dwtr.step/ucc3895dwtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (61 pp, sha256
839591a78c6304d9, retrieved 2026-09-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).