6N137
Public Made by Adomby adom
Everlight Elec Logic Output Optoisolators, DIP-8. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdown6N137
3D generated from the datasheet; KiCad's model does not fit this maker's body.
Everlight Elec · Logic Output Optoisolators · DIP-8
6N137 from Everlight Elec, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol and footprint from KiCad-official CAD; the 3D model is generated from the datasheet's package dimensions.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | No Connection | no_connect | No connection. |
| 2 | Anode | passive | Input LED anode. |
| 3 | Cathode | passive | Input LED cathode. |
| 4 | No Connection | no_connect | No connection. |
| 5 | Gnd | power_in | Output-side ground. A 0.1 µF bypass capacitor must be connected between pins 8 and 5. |
| 6 | Vout | output | Logic gate output (open collector). |
| 7 | VE | input | Enable input (Enable input voltage not to exceed VCC). |
| 8 | VCC | power_in | Output-side supply (max 7.0 V). Bypass 0.1 µF to pin 5. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Everlight Elec |
| Package | DIP-8 |
| Category | Optoisolators |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward current | IF | 50 | mA | 2 | |||
| Enable input voltage | VE | 5.5 | V | Not exceed VCC by more than 500mV | 2 | ||
| Reverse voltage | VR | 5 | V | 2 | |||
| Power dissipation (input) | PD | 100 | mW | 2 | |||
| Power dissipation (output) | PC | 85 | mW | 2 | |||
| Output current | IO | 50 | mA | 2 | |||
| Output voltage | VO | 7 | V | 2 | |||
| Supply voltage | VCC | 7 | V | 2 | |||
| Output power dissipation | PO | 100 | mW | 2 | |||
| Isolation voltage | VISO | 5000 | V rms | AC for 1 minute, R.H.=40~60% R.H. | 2 | ||
| Operating temperature | TOPR | -40 | 85 | °C | 2 | ||
| Storage temperature | TSTG | -55 | 125 | °C | 2 | ||
| Soldering temperature | TSOL | 260 | °C | For 10 seconds | 2 | ||
| Forward voltage | VF | 1.4 | 1.8 | V | IF = 10mA | 3 | |
| Reverse voltage | VR | 5 | V | IR = 10μA | 3 | ||
| High level supply current | ICCH | 7 | 10 | mA | IF=0mA, VE=0.5V, VCC=5.5V | 3 | |
| Low level supply current | ICCL | 9 | 13 | mA | IF=10mA, VCC=5.5V | 3 | |
| High level enable voltage | VEH | 2 | V | IF=10mA, VCC=5.5V | 3 | ||
| Low level enable voltage | VEL | 0.8 | V | IF=10mA, VCC=5.5V | 3 | ||
| HIGH level output current | IOH | 2.1 | 100 | uA | VCC=5.5V, VO=5.5V, IF=250μA, VE=2.0V | 3 | |
| LOW level output voltage | VOL | 0.35 | 0.6 | V | VCC = 5.5V, IF=5mA, VE=2.0V, ICL=13mA | 3 | |
| Input threshold current | IFT | 2.5 | 5 | mA | VCC= 5.5V, VO=0.6V, VE =2.0V, IOL=13mA | 3 | |
| Propagation delay time to output high level | TPHL | 35 | 75 | ns | CL = 15pF, RL=350Ω, TA=25°C | 4 | |
| Propagation delay time to output low level | TPLH | 40 | 75 | ns | CL = 15pF, RL=350Ω, TA=25°C | 4 | |
| Pulse width distortion | /Tphl, Tplh/ | 5 | 35 | ns | CL = 15pF, RL=350Ω | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 1.1 (A) Maximum Body Case Temperature Profile for evaluation of Reflow Profile Note: Reference: IPC/JEDEC J-STD-020D | 14 |
CAD (land: KiCad; 3D: generated from the datasheet)
- Symbol:
6N137 - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8, generated on the KiCad land (body 6.6 x 9.76 mm, terminals on the pads, 4.5 mm tall, datasheet A, nominal). KiCad's stock model for this land is taller than the datasheet allows, so the model is generated from the datasheet drawing; the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
- 3D model files:
6n137-everlight-etched.step/6n137-everlight-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);6n137-everlight.step/6n137-everlight.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Everlight Elec datasheet (15 pp, sha256
a59e01429a38970a, retrieved 2026-11-13, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: land: KiCad official libraries (CC-BY-SA 4.0); 3D: generated from the datasheet's package dimensions (provenance.model_3d_generated).
Same part number, other makers
This page is 6N137 by Everlight Elec. These makers sell a part under the same number; each is a different part with its own datasheet and page: