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MG32F103RBT6
Public Made by Adomby adom
Megawin Tech Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMG32F103RBT6
Megawin Tech · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
MG32F103RBT6 from Megawin Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply input, 1.8 V to 3.6 V, which powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off. |
| 2 | PC13 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate function TAMPER/RTC. |
| 3 | PC14 | bidirectional | General-purpose I/O (max 16 mA per pin), with the OSC32_IN function for the 32.768 kHz LSE crystal. |
| 4 | PC15 | bidirectional | General-purpose I/O (max 16 mA per pin), with the OSC32_OUT function for the 32.768 kHz LSE crystal. |
| 5 | PD0 | bidirectional | General-purpose I/O (max 16 mA per pin), with the OSC_IN function for the 4 to 16 MHz HSE crystal. |
| 6 | PD1 | bidirectional | General-purpose I/O (max 16 mA per pin), with the OSC_OUT function for the 4 to 16 MHz HSE crystal. |
| 7 | NRST | input | External reset pin, active low, which triggers a system reset when driven low. |
| 8 | PC0 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions I2S_WS, SPIM2_NSS0, SPIS2_NSS and analog input ADC_IN10. |
| 9 | PC1 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions I2S_SCLK, SPIM2_SCK, SPIS2_SCK and analog input ADC_IN11. |
| 10 | PC2 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions I2S_SD0, SPIM2_MI, SPIS2_SO and analog input ADC_IN12. |
| 11 | PC3 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions I2S_SD1, SPIM2_MO, SPIS2_SI and analog input ADC_IN13. |
| 12 | VSSA | power_in | Analog ground for the ADC; must be connected to the same ground system as the other VSS pins. |
| 13 | VDDA | power_in | Analog supply for the ADC, 2.4 V to 3.6 V while the ADC operates; the datasheet recommends using the same supply for VDD and VDDA. |
| 14 | PA0 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH1_ETR, UART2_CTS, WKUP (a rising edge exits Standby mode) and analog input ADC_IN0. |
| 15 | PA1 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH2, UART2_RTS and analog input ADC_IN1. |
| 16 | PA2 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH3, UART2_TX and analog input ADC_IN2. |
| 17 | PA3 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH4, UART2_RX and analog input ADC_IN3. |
| 18 | VSS_4 | power_in | Digital ground pin; all VSS pins must be connected to the external supply system, with a maximum difference of 50 mV between ground pins. |
| 19 | VDD_4 | power_in | Digital supply for I/O pins and the internal LDO, 2.0 V to 3.6 V; all VDD pins must be connected to the supply system. |
| 20 | PA4 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions QSPI_NSS0, SPIS1_NSS, UART2_CK and analog input ADC_IN4. |
| 21 | PA5 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions QSPI_SCK, SPIS1_SCK and analog input ADC_IN5. |
| 22 | PA6 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_BKIN, TIM3_CH1, QSPI_MI_IO1, SPIS1_SO and analog input ADC_IN6. |
| 23 | PA7 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH1N, TIM3_CH2, QSPI_MO_IO0, SPIS1_SI and analog input ADC_IN7. |
| 24 | PC4 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate function TRACECK and analog input ADC_IN14. |
| 25 | PC5 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions SPIM2_NSS2, TRACED0 and analog input ADC_IN15. |
| 26 | PB0 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH2N, TIM3_CH3, I2S_MCLK, QSPI_IO2 and analog input ADC_IN8. |
| 27 | PB1 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH3N, TIM3_CH4, QSPI_IO3 and analog input ADC_IN9. |
| 28 | PB2 | bidirectional | General-purpose I/O (max 16 mA per pin), which also serves as the BOOT1 boot-mode select pin sampled at startup. |
| 29 | PB10 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH3, TIM4_CH1, I2C2_SCL, QSPI_NSS2, UART3_TX. |
| 30 | PB11 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH4, I2C2_SDA, SPIM2_NSS1, UART3_RX. |
| 31 | VSS_1 | power_in | Digital ground pin; all VSS pins must be connected to the external supply system. |
| 32 | VDD_1 | power_in | Digital supply for I/O pins and the internal LDO, 2.0 V to 3.6 V; all VDD pins must be connected to the supply system. |
| 33 | PB12 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_BKIN, I2S_WS, LED4, SPIM2_NSS0, SPIS2_NSS, UART3_CK. |
| 34 | PB13 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH1N, I2S_SCLK, LED5, SPIM2_SCK, SPIS2_SCK, UART3_CTS. |
| 35 | PB14 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH2N, LED6, SPIM2_MI, SPIS2_SO, UART3_RTS. |
| 36 | PB15 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH3N, LED7, SPIM2_MO, SPIS2_SI, I2S_SD0. |
| 37 | PC6 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH1, I2S_MCLK, LED0. |
| 38 | PC7 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH2, I2S_MCLK, LED1. |
| 39 | PC8 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH3, LED2. |
| 40 | PC9 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH4, LED3, TRACED1. |
| 41 | PA8 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH1, LED0, UART1_CK, MCO and analog comparator input CMPA_P0. |
| 42 | PA9 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH2, LED1, UART1_TX and analog comparator input CMPA_N0. |
| 43 | PA10 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH3, LED2, UART1_RX. |
| 44 | PA11 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_CH4, LED3, UART1_CTS and the USB D- signal USBDM. |
| 45 | PA12 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM1_ETR, UART1_RTS and the USB D+ signal USBDP. |
| 46 | PA13 | bidirectional | General-purpose I/O (max 16 mA per pin), with the SWDIO debug data function, alternate function QSPI_NSS1 and analog comparator input CMPA_P3. |
| 47 | VSS_2 | power_in | Digital ground pin; all VSS pins must be connected to the external supply system. |
| 48 | VDD_2 | power_in | Digital supply for I/O pins and the internal LDO, 2.0 V to 3.6 V; all VDD pins must be connected to the supply system. |
| 49 | PA14 | bidirectional | General-purpose I/O (max 16 mA per pin), with the SWDCLK debug clock function, alternate function QSPI_NSS2 and analog comparator input CMPA_N3. |
| 50 | PA15 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM2_CH1_ETR, I2S_WS, I2C1_SMBAI, QSPI_NSS0, SPIS1_NSS and analog comparator input CMPB_P3. |
| 51 | PC10 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions LED4, UART3_TX, TRACED2 and analog comparator input CMPB_P1. |
| 52 | PC11 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions LED5, UART3_RX, TRACED3 and analog comparator input CMPB_P2. |
| 53 | PC12 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM4_ETR, LED6, UART3_CK and analog comparator input CMPB_N0. |
| 54 | PD2 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_ETR, LED7 and analog comparator input CMPB_P0. |
| 55 | PB3 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions SWO, TIM2_CH2, I2S_SCLK, QSPI_SCK, SPIS1_SCK and analog comparator input CMPB_N3. |
| 56 | PB4 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH1, QSPI_MI_IO1, SPIS1_SO and analog comparator input CMPA_P1. |
| 57 | PB5 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM3_CH2, I2S_SD1, I2C1_SMBAI, QSPI_MO_IO0, SPIS1_SI and analog comparator input CMPA_P2. |
| 58 | PB6 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM4_CH1, I2C1_SCL, QSPI_NSS1, UART1_TX and analog comparator input CMPA_N1. |
| 59 | PB7 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM4_CH2, I2C1_SDA, SPIM2_NSS1, UART1_RX and analog comparator input CMPA_N2. |
| 60 | BOOT0 | input | Boot-mode select pin sampled at startup to choose between user Flash, system memory and internal SRAM boot. |
| 61 | PB8 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM4_CH3, I2C1_SCL, SPIM2_NSS2, UART1_CTS and analog comparator input CMPB_N1. |
| 62 | PB9 | bidirectional | General-purpose I/O (max 16 mA per pin), with alternate functions TIM4_CH4, I2C1_SDA, UART1_RTS and analog comparator input CMPB_N2. |
| 63 | VSS_3 | power_in | Digital ground pin; all VSS pins must be connected to the external supply system. |
| 64 | VDD_3 | power_in | Digital supply for I/O pins and the internal LDO, 2.0 V to 3.6 V; all VDD pins must be connected to the supply system. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Megawin Tech |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD-VSS external main supply voltage (including VDDA and VDD) | VDD-VSS | -0.5 | 3.6 | V | 24 | ||
| Voltage difference between different supply pins | /ΔVDDx/ | 50 | mV | 24 | |||
| Voltage difference between different ground pins | /VSSx-VSS/ | 50 | mV | 24 | |||
| Total current through VDD/VDDA supply lines (supply current) | IVDD | 60 | mA | 24 | |||
| Total current through VSS ground lines (sink current) | IVSS | 60 | mA | 24 | |||
| Output sink current on any I/O and control pin | IIO | 16 | mA | 24 | |||
| Output source current on any I/O and control pin | IIO | -16 | mA | 24 | |||
| Injection current on a pin | IINJ(PIN) | -5 | 5 | mA | 24 | ||
| Sum of injection currents on pins | ΣIINJ(PIN) | -25 | 25 | mA | 24 | ||
| Storage temperature range | TSTG | -45 | 150 | °C | 25 | ||
| Maximum junction temperature | TJ | 100 | °C | 25 | |||
| Internal AHB clock frequency | fHCLK | 72 | MHz | 25 | |||
| Internal APB1 clock frequency | fPCLK1 | 72 | MHz | 25 | |||
| Internal APB2 clock frequency | fPCLK2 | 72 | MHz | 25 | |||
| Standard operating voltage | VDD | 2 | 3.6 | V | 25 | ||
| Analog operating voltage | VDDA | 2 | 3.6 | V | 25 | ||
| Backup-domain operating voltage | VBAT | 1.8 | 3.6 | V | 25 | ||
| Operating temperature | T | -40 | 85 | °C | 25 | ||
| External HSE clock frequency | fHSEext | 8 | 16 | MHz | 28 | ||
| HSE input high/low level time | TW(HSE) | 16 | ns | 28 | |||
| HSE rise/fall time | Tr(HSE)/Tf(HSE) | 5 | ns | 28 | |||
| HSE duty cycle | DuCy(HSE) | 45 | 55 | % | 28 | ||
| LSE input high/low level time | TW(LSE) | 450 | ns | 28 | |||
| LSE duty cycle | DuCy(LSE) | 30 | 70 | % | 28 | ||
| Internal fast clock 0 (MHSI) duty cycle | DuCy(MHSI) | 45 | 55 | % | 29 | ||
| Internal fast clock 0 (MHSI) oscillator startup time | TSU(MHSI) | 1 | 2 | us | VSS ≤ Vin ≤ VDD | 29 | |
| Internal fast clock 1 (FHSI) duty cycle | DuCy(FHSI) | 45 | 55 | % | 29 | ||
| Internal fast clock 1 (FHSI) oscillator startup time | TSU(FHSI) | 200 | 500 | ns | VSS ≤ Vin ≤ VDD | 29 | |
| Internal slow clock (LSI) frequency | fLSI | 20 | 40 | KHz | 29 | ||
| PLL input clock frequency | fPLLIN | 1 | 8 | 16 | MHz | 30 | |
| PLL input clock duty cycle | PLL input duty | 40 | 60 | % | 30 | ||
| PLL lock time | TLOCK | 200 | us | 30 | |||
| Flash page program current | IDDPROG | 2 | mA | 30 | |||
| Flash page/chip erase current | IDDERASE | 1.5 | mA | 30 | |||
| Flash read current at 48 MHz | IDDREAD | 4.7 | mA | @48MHz | 30 | ||
| Flash endurance (erase/write cycles) | NEND | 100 | 千次 | 30 | |||
| Data retention time | tRET | 10 | year | 30 | |||
| ESD human body model voltage | VESD(HBM) | 4000 | V | TA = +25 ◦C, conforms to JEDEC JS-001-2017 | 31 | ||
| ESD charged device model voltage | VESD(CDM) | 500 | V | TA = +25 ◦C, conforms to JEDEC JS-002-2018 | 31 | ||
| Input low voltage | VIL | -0.5 | V | 32 | |||
| Input leakage current | Ilkg | -1 | 1 | uA | VSS ≤ Vin ≤ VDD | 32 | |
| Weak pull-up equivalent resistance | Rpu | 30 | 40 | 50 | kΩ | Vin=VSS | 32 |
| Weak pull-down equivalent resistance | Rpd | 30 | 40 | 50 | kΩ | Vin=VDD | 32 |
| Maximum output frequency, speed x0 | fmax(IO)out | 10 | MHz | CL=50pF,VDD=2V to 3.6V | 32 | ||
| Maximum output frequency, speed x1 | fmax(IO)out | 50 | MHz | CL=50pF,VDD=2V to 3.6V | 32 | ||
| High-to-low output time, speed x1 | tf(IO)out | 25 | ns | CL=50pF,VDD=2V to 3.6V | 32 | ||
| Low-to-high output time, speed x1 | tr(IO)out | 25 | ns | CL=50pF,VDD=2V to 3.6V | 32 | ||
| Comparator input voltage | Vin | 0.6 | V | 33 | |||
| Comparator hysteresis | VHYST | 2 | 5 | mV | 33 | ||
| Comparator input offset voltage | VOFF | 5 | 15 | mV | 33 | ||
| Comparator propagation delay | TPGD | 200 | nS | 33 | |||
| Comparator average operating current | Iq | 8.5 | uA | 33 | |||
| Timer resolution unit | Tres(TIM) | 1 | TTIMxCLK | 32 | |||
| Timer resolution | RESTIM | 20 | bit | 32 | |||
| ADC supply voltage | VDDA | 2.4 | 3.6 | V | 33 | ||
| ADC sampling rate | fs | 0.05 | 1 | MHz | 33 | ||
| External trigger frequency | fTRIG | 823 | KHz | fADC =14MHz | 33 | ||
| External input impedance | RAIN | 200 | Ω | 33 | |||
| ADC conversion rate (12-bit) | FCONV | 940 | KSPS | 12-bit | 33 | ||
| ADC conversion voltage range | VAIN | 0 | V | 33 |
CAD (KiCad official)
- Symbol:
MG32F103RBT6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
mg32f103rbt6-etched.step/mg32f103rbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mg32f103rbt6.step/mg32f103rbt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Megawin Tech datasheet (41 pp, sha256
d60b1d138834b89b, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).