KSZ8463RLI from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RXM1	bidirectional	Port 1 physical receive (MDI) or transmit (MDI-X) signal, negative differential.
2	RXP1	bidirectional	Port 1 physical receive (MDI) or transmit (MDI-X) signal, positive differential.
3	AGND	power_in	Analog ground.
4	TXM1	bidirectional	Port 1 physical transmit (MDI) or receive (MDI-X) signal, negative differential.
5	TXP1	bidirectional	Port 1 physical transmit (MDI) or receive (MDI-X) signal, positive differential.
6	VDD_AL	power_in	Low-voltage analog power input, to be filtered with a ferrite bead and capacitors.
7	ISET	output	Sets the PHY transmit output current; pull down with a 6.49 kΩ (1%) resistor to ground.
8	AGND	power_in	Analog ground.
9	VDD_A3.3	power_in	3.3 V analog VDD input power supply; must be well decoupled.
10	RXM2	bidirectional	Port 2 physical receive (MDI) or transmit (MDI-X) signal, negative differential.
11	RXP2	bidirectional	Port 2 physical receive (MDI) or transmit (MDI-X) signal, positive differential.
12	AGND	power_in	Analog ground.
13	TXM2	bidirectional	Port 2 physical transmit (MDI) or receive (MDI-X) signal, negative differential.
14	TXP2	bidirectional	Port 2 physical transmit (MDI) or receive (MDI-X) signal, positive differential.
15	FXSD2	input	Fiber signal detect input for port 2 in 100BASE-FX mode; must be pulled to GND in copper mode and is available only on KSZ8463FML/FRL.
16	VDD_COL	power_in	Second low-voltage analog power input, to be filtered with a ferrite bead and capacitors.
17	PWRDN	input	Active-low full-chip power-down (low = power-down, high or floating = normal); while low, all I/O are tri-stated and registers return to default.
18	X1	input	25 MHz crystal or oscillator input with ±50 ppm clock requirement; on the KSZ8463RL it can instead take a 50 MHz REFCLK_I selected by pin 41 at power-up.
19	X2	output	Crystal connection; left as no connect when an oscillator drives X1.
20	DGND	power_in	Digital ground.
21	VDD_IO	power_in	3.3 V, 2.5 V, or 1.8 V digital I/O supply, also the input to the internal low-voltage regulator.
22	TX_EN	input	RMII transmit enable; active high indicates valid transmit data on TXD[1:0].
23	TXD3/EN_REFCLKO	input	In RMII mode, pulling this pin up enables the 50 MHz REFCLK_O output on pin 32 and pulling it down disables it.
24	TXD2/NC	input	No connect in RMII mode (not used).
25	TXD1	input	RMII transmit data bit 1, synchronous to the 50 MHz REFCLK.
26	TXD0	input	RMII transmit data bit 0, synchronous to the 50 MHz REFCLK.
27	TX_CLK/REFCLK_I	bidirectional	In RMII mode, the 50 MHz reference clock input (internal or external source).
28	TX_ER/MII_BP	input	No connect in RMII mode (not used).
29	DGND	power_in	Digital ground.
30	VDD_IO	power_in	3.3 V, 2.5 V, or 1.8 V digital I/O supply, also the input to the internal low-voltage regulator.
31	RX_DV	bidirectional	RMII receive data valid, active high indicates RXD[1:0] is valid; the power-up pull-up/no-connect or pull-down level selects PHY or MAC MII mode in MII operation.
32	RXD3/REFCLK_O	bidirectional	In RMII mode, outputs the 50 MHz REFCLK_O clock when EN_REFCLKO (pin 23) is pulled up, with 16 mA drive.
33	RXD2	bidirectional	Not used in RMII mode; at power-up/reset the pull-up/no-connect selects high-speed SPI (up to 50 MHz) and pull-down selects low-speed SPI (up to 12.5 MHz).
34	RXD1	bidirectional	RMII receive data bit 1, synchronous to the 50 MHz REFCLK; latched with RXD0 at power-up to select the serial bus mode.
35	RXD0	bidirectional	RMII receive data bit 0, synchronous to the 50 MHz REFCLK; latched with RXD1 at power-up to select the serial bus mode (default SPI slave).
36	CRS/GPIO9_RLI	bidirectional	In RMII mode this pin is GPIO9 (internal pull-down), see GPIO0 pin 48 description.
37	COL/GPIO10_RLI	bidirectional	In RMII mode this pin is GPIO10 (internal pull-down), see GPIO0 pin 48 description.
38	RX_CLK/GPIO7_RLI	bidirectional	In RMII mode this pin is GPIO7 (internal pull-down), see GPIO0 pin 48 description.
39	DGND	power_in	Digital ground.
40	VDD_L	power_in	Low-voltage core connection: a low-voltage input when the internal regulator is not used, or the low-voltage output when it is used.
41	SPI_DO	bidirectional	SPI slave data output (high-impedance when SPI_CSN is high); its power-up level selects 25 MHz from X1/X2 (pull-up) or 50 MHz from REFCLK_I (pull-down, KSZ8463RL/FRL only).
42	SPI_CSN	input	Active-low chip select for SPI slave mode; requires an external 4.7 kΩ pull-up when in use.
43	INTRN	output	Active-low interrupt output to the host CPU; requires an external 4.7 kΩ pull-up.
44	SPI_SCLK/MDC	input	SPI slave serial clock input in SPI mode, or MIIM MDC clock input in MIIM mode.
45	SPI_DI/MDIO	bidirectional	SPI slave serial data input in SPI mode, or MIIM MDIO data input/output; requires an external 4.7 kΩ pull-up.
46	GPIO8	bidirectional	General purpose I/O 8 (internal pull-down), see GPIO0 pin 48 description.
47	GPIO11	bidirectional	General purpose I/O 11 (internal pull-up), see GPIO0 pin 48 description.
48	GPIO0	bidirectional	General purpose I/O 0 usable for IEEE 1588 event trigger or time stamp capture, synchronized to the internal 1588 clock and directly drivable or readable by the host.
49	GPIO1	bidirectional	General purpose I/O 1 (internal pull-up), see GPIO0 pin 48 description.
50	DGND	power_in	Digital ground.
51	VDD_L	power_in	Low-voltage core connection: a low-voltage input when the internal regulator is not used, or the low-voltage output when it is used.
52	GPIO2	bidirectional	General purpose I/O 2 (internal pull-up), see GPIO0 pin 48 description.
53	GPIO3	bidirectional	General purpose I/O 3 (internal pull-down), see GPIO0 pin 48 description.
54	GPIO4	bidirectional	General purpose I/O 4 (internal pull-down), see GPIO0 pin 48 description.
55	GPIO5	bidirectional	General purpose I/O 5 (internal pull-down), see GPIO0 pin 48 description.
56	VDD_IO	power_in	3.3 V, 2.5 V, or 1.8 V digital I/O supply, also the input to the internal low-voltage regulator.
57	DGND	power_in	Digital ground.
58	GPIO6	bidirectional	General purpose I/O 6 (internal pull-up), see GPIO0 pin 48 description.
59	P1LED1/GPIO7_MLI	bidirectional	Programmable active-low LED output for port 1 activity/status (LED on when low); in RMII mode this pin is P1LED1.
60	P1LED0	bidirectional	Programmable LED output for port 1 status, active low (LED on when low), with internal pull-up.
61	P2LED1/GPIO9_MLI	bidirectional	Programmable LED output for port 2 activity/status, active low; in RMII mode this pin is P2LED1.
62	P2LED0/GPIO10_MLI	bidirectional	Programmable LED output for port 2 status, active low; in RMII mode this pin is P2LED0.
63	RSTN	input	Active-low hardware reset input; must be held low for at least 10 ms after VDD_IO and 3.3 V are stable.
64	FXSD1	input	Fiber signal detect input for port 1 in 100BASE-FX mode; must be pulled to GND in copper mode and is available only on KSZ8463FML/FRL.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-64(10x10)
Category	Communication Interface Chip/UART/485/232
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD_A3.3, VDD_IO)		-0.5		5	V		189
Supply Voltage (VDD_AL, VDD_L)		-0.5		1.8	V		189
Input Voltage (All Inputs)		-0.5		5	V		189
Output Voltage (All Outputs)		-0.5		5	V		189
Lead Temperature				260	°C	soldering, 10 s	189
Storage Temperature	TS	-65		150	°C		189
Maximum Junction Temperature	TJ			125	°C		189
HBM ESD Rating				2	kV	HBM	189
Supply Voltage VDDA_3.3	VDDA_3.3	3.135		3.465	V		189
Supply Voltage VDD_L, VDD_AL, VDD_COL	VDD_L, VDD_AL, VDD_COL	1.25		1.4	V		189
Supply Voltage VDD_IO (3.3V)	VDD_IO	3.135		3.465	V	3.3V I/O	189
Supply Voltage VDD_IO (2.5V)	VDD_IO	2.375		2.625	V	2.5V I/O	189
Supply Voltage VDD_IO (1.8V)	VDD_IO	1.71		1.89	V	1.8V I/O	189
Ambient Operating Temperature (Industrial)	TA	-40		85	°C	Industrial	189
Reference crystal/oscillator clock frequency tolerance		-50		50	ppm	25 MHz on X1/X2 crystal or oscillator	11
CMOS Input High Voltage	VIH	2.1			V	VDD_IO = 3.3V	191
CMOS Input High Voltage	VIH	1.7			V	VDD_IO = 2.5V	191
CMOS Input High Voltage	VIH	1.3			V	VDD_IO = 1.8V	191
CMOS Input Low Voltage	VIL			0.9	V	VDD_IO = 3.3V	191
CMOS Input Low Voltage	VIL			0.6	V	VDD_IO = 1.8V	191
Input Current	IIN	-10		10	µA	VIN = GND ~ VDD_IO	191
X1 Crystal/Osc Input High Voltage	VIH	2.1			V	VDD_A3.3 = 3.3V, VDD_IO = any	191
X1 Crystal/Osc Input Low Voltage	VIL			0.9	V	VDD_A3.3 = 3.3V, VDD_IO = any	191
X1 Crystal/Osc Input Current	IIN			10	µA		191
PWRDN Input High Voltage	VIH	1.1			V	VDD_A3.3 = 3.3V, VDD_IO = any	191
PWRDN Input Low Voltage	VIL			0.3	V	VDD_A3.3 = 3.3V, VDD_IO = any	192
FXSD Input High Voltage	VIH	2.1			V	VDD_A3.3 = 3.3V, VDD_IO = any	192
FXSD Input Low Voltage	VIL			1.2	V	VDD_A3.3 = 3.3V, VDD_IO = any	192
CMOS Output High Voltage	VOH	2.4			V	IOH = -8 mA; VDD_IO = 3.3V	192
CMOS Output High Voltage	VOH	1.9			V	IOH = -8 mA; VDD_IO = 2.5V	192
CMOS Output High Voltage	VOH	1.5			V	IOH = -8 mA; VDD_IO = 1.8V	192
CMOS Output Low Voltage	VOL			0.4	V	VIOL = 8 mA; VDD_IO = 3.3V	192
CMOS Output Low Voltage	VOL			0.2	V	VIOL = 8 mA; VDD_IO = 1.8V	192
Output Tri-State Leakage	/IOZ/			10	µA		192
100BASE-TX Peak Differential Output Voltage	VO	0.95		1.05	V	100Ω termination on the diff. output; printed ±0.95 / ±1.05	192
100BASE-TX Output Voltage Imbalance	VIMB			2	%	100Ω termination on the diff. output	192
100BASE-TX Rise/Fall Time	tr/tf	3		5	ns		192
100BASE-TX Rise/Fall Time Imbalance			0	0.5	ns		192
100BASE-TX Duty Cycle Distortion		-0.25		0.25	ns		192
100BASE-TX Overshoot				5	%		192
100BASE-TX Output Jitter			0.7	1.4	ns	Peak-to-peak	192
100BASE-TX Jitter Added				3.5	ns	100Ω termination on the differential output (peak-to-peak)	192
10BASE-T Peak Differential Output Voltage	VP	2.2	2.5	2.8	V	100Ω termination on the differential output	192
1.8V Pull-Up Resistance	R1.8PU	57	100	187	kΩ	VDD_IO = 1.8V	192
1.8V Pull-Down Resistance	R1.8PD	55	100	190	kΩ	VDD_IO = 1.8V	192
2.5V Pull-Up Resistance	R2.5PU	37	59	102	kΩ	VDD_IO = 2.5V	192
2.5V Pull-Down Resistance	R2.5PD	35	60	110	kΩ	VDD_IO = 2.5V	192
3.3V Pull-Up Resistance	R3.3PU	29	43	70	kΩ	VDD_IO = 3.3V	192
3.3V Pull-Down Resistance	R3.3PD	27	43	76	kΩ	VDD_IO = 3.3V	192
ISET Resistor Tolerance		-1		1	%	External ISET pull-down resistor (printed 1%)	10
ISET External Resistor			6.49		kΩ	Pull-down on ISET to ground	10
Crystal Effective Series Resistance				50	Ω	Typical reference crystal, 25 MHz	205
Junction-to-Ambient Thermal Resistance	ΘJA		49		°C/W	No heat spreader; 0 m/s air velocity	189
Junction-to-Case Thermal Resistance	ΘJC		19		°C/W	No heat spreader; 0 m/s air velocity	189

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		In copper mode, and on the KSZ8463ML and KSZ8463RL, the FXSD pins are unused and should be pulled low.	18

CAD (KiCad official)

Symbol: KSZ8463RLI
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ksz8463rli-etched.step / ksz8463rli-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8463rli.step / ksz8463rli.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (213 pp, sha256 6e2255020c924402, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

KSZ8463RLI

Verified KSZ8463RLI

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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