component
GD25LQ16EEIGR
Public Made by Adomby adom
GigaDevice(兆易创新) NOR FLASH, USON-8(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownGD25LQ16EEIGR
GigaDevice(兆易创新) · NOR FLASH · USON-8(2x3)
GD25LQ16EEIGR from GigaDevice(兆易创新), in a USON-8(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select Input; it must be driven high when the chip is not selected and must not be left floating at any time after power is on. |
| 2 | SO (IO1) | bidirectional | Data Output (Data Input Output 1), used as the serial data output in standard SPI and as IO1 in Dual/Quad SPI. |
| 3 | WP# (IO2) | bidirectional | Write Protect Input (Data Input Output 2), serving as IO2 in Quad SPI mode. |
| 4 | VSS | power_in | Ground. |
| 5 | SI (IO0) | bidirectional | Data Input (Data Input Output 0), used as the serial data input in standard SPI and as IO0 in Dual/Quad SPI. |
| 6 | SCLK | input | Serial Clock Input. |
| 7 | HOLD# (IO3) | bidirectional | Hold Input (Data Input Output 3), serving as IO3 in Quad SPI mode. |
| 8 | VCC | power_in | Power Supply pin; the part is specified for a single supply with full voltage range 1.65-2.1V (stated in the Features section, page 4). |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice(兆易创新) |
| Package | USON-8(2x3) |
| Category | Memory |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Leakage Current | ILI | -2 | 2 | μA | 48 | ||
| Output Leakage Current | ILO | -2 | 2 | μA | 48 | ||
| Standby Current | ICC1 | 10 | 25 | μA | CS#=VCC, VIN=VCC or VSS | 48 | |
| Deep Power-Down Current | ICC2 | 1 | 8 | μA | CS#=VCC, VIN=VCC or VSS | 48 | |
| Operating Current (Read) | ICC3 | 10 | 15 | mA | CLK=0.1VCC / 0.9VCC at 133MHz, Q=Open(x4 I/O) | 48 | |
| Operating Current (Read) | ICC3 | 8 | 12 | mA | CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(x4 I/O) | 48 | |
| Operating Current (Read) | ICC3 | 3 | 5 | mA | CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(x1 I/O) | 48 | |
| Operating Current (PP) | ICC4 | 8 | 15 | mA | CS#=VCC | 48 | |
| Operating Current (WRSR) | ICC5 | 8 | 15 | mA | CS#=VCC | 48 | |
| Operating Current (SE) | ICC6 | 8 | 15 | mA | CS#=VCC | 48 | |
| Operating Current (BE) | ICC7 | 8 | 15 | mA | CS#=VCC | 48 | |
| Operating Current (CE) | ICC8 | 8 | 15 | mA | CS#=VCC | 48 | |
| Output Low Voltage | VOL | 0.2 | V | IOL = 100μA | 48 | ||
| Ambient Operating Temperature (I grade) | TA | -40 | 85 | ℃ | Value for I grade (-40℃ to +85℃) only | 46 | |
| Storage Temperature | -65 | 150 | ℃ | 46 | |||
| Transient Input/Output Voltage (note: overshoot) | -2 | V | Printed upper limit is VCC+2.0 V, not a number | 46 | |||
| Applied Input/Output Voltage | -0.6 | V | Printed upper limit is VCC+0.4 V, not a number | 46 | |||
| Supply Voltage | VCC | -0.6 | 2.5 | V | 46 | ||
| Supply Voltage (operating range) | VCC | 1.65 | 2.1 | V | TA = -40℃~85℃ (table header) | 48 | |
| Clock Low To Output Valid (CL = 30pF) | tCLQV | 7 | ns | CL = 30pF | 51 | ||
| Write Inhibit Voltage | VWI | 1.4 | V | 46 | |||
| VCC (min.) to device operation | tVSL | 700 | μs | 46 | |||
| Input Capacitance | CIN | 6 | pF | VIN=0V | 47 | ||
| Output Capacitance | COUT | 8 | pF | VOUT=0V | 47 | ||
| Serial Clock Frequency | fC | 133 | MHz | all commands except 03H | 51 | ||
| Serial Clock Frequency (Read) | fR | 80 | MHz | Read (03H) | 51 | ||
| Serial Clock Rise Time (Slew Rate) | tCLCH | 0.2 | V/ns | 51 | |||
| Serial Clock Fall Time (Slew Rate) | tCHCL | 0.2 | V/ns | 51 | |||
| CS# Active Setup Time | tSLCH | 5 | ns | 51 | |||
| CS# Active Hold Time | tCHSH | 5 | ns | 51 | |||
| CS# Not Active Setup Time | tSHCH | 5 | ns | 51 | |||
| CS# Not Active Hold Time | tCHSL | 5 | ns | 51 | |||
| CS# High Time (Read/Write) | tSHSL | 20 | ns | Read/Write | 51 | ||
| Output Disable Time | tSHQZ | 6 | ns | 51 | |||
| Output Hold Time | tCLQX | 1.2 | ns | 51 | |||
| Data In Setup Time | tDVCH | 2 | ns | 51 | |||
| Data In Hold Time | tCHDX | 2 | ns | 51 | |||
| HOLD# Low Setup Time (Relative To Clock) | tHLCH | 5 | ns | 51 | |||
| HOLD# High Setup Time (Relative To Clock) | tHHCH | 5 | ns | 51 | |||
| HOLD# Low Hold Time (Relative To Clock) | tCHHH | 5 | ns | 51 | |||
| HOLD# High Hold Time (Relative To Clock) | tCHHL | 5 | ns | 51 | |||
| HOLD# Low To High-Z Output | tHLQZ | 6 | ns | 51 | |||
| HOLD# High To Low-Z Output | tHHQX | 6 | ns | 51 | |||
| Write Protect Setup Time Before CS# Low | tWHSL | 20 | ns | 51 | |||
| Write Protect Hold Time After CS# High | tSHWL | 100 | ns | 51 | |||
| CS# High To Deep Power-Down Mode | tDP | 3 | μs | 51 | |||
| CS# High To Standby Mode Without Electronic Signature Read | tRES1 | 20 | μs | 51 | |||
| CS# High To Standby Mode With Electronic Signature Read | tRES2 | 20 | μs | 51 | |||
| CS# High To Next Command After Suspend | tSUS | 20 | μs | 51 | |||
| Latency Between Resume And Next Suspend | tRS | 100 | μs | 51 | |||
| CS# High To Next Command After Reset (Except From Erase) | tRST | 30 | μs | Except From Erase | 51 | ||
| CS# High To Next Command After Reset (From Erase) | tRST_E | 12 | ms | From Erase | 51 | ||
| Write Status Register Cycle Time | tW | 2 | 25 | ms | 52 | ||
| Byte Program Time (First Byte) | tBP1 | 30 | 60 | μs | 52 | ||
| Additional Byte Program Time (After First Byte) | tBP2 | 2.5 | 5 | μs | 52 | ||
| Page Programming Time | tPP | 0.4 | 2.4 | ms | 52 | ||
| Sector Erase Time | tSE | 40 | 300 | ms | 52 | ||
| Block Erase Time (32K Bytes) | tBE1 | 0.15 | 0.8 | s | 52 | ||
| Block Erase Time (64K Bytes) | tBE2 | 0.2 | 1.2 | s | 52 | ||
| Chip Erase Time (GD25LQ16E) | tCE | 4.5 | 10 | s | 52 |
CAD (KiCad official)
- Symbol:
GD25LQ16EEIGR - Footprint:
Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm - 3D model: USON-8(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gd25lq16eeigr-etched.step/gd25lq16eeigr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd25lq16eeigr.step/gd25lq16eeigr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice(兆易创新) datasheet (68 pp, sha256
b1378f6aac83c294, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).