component
TPS40200D
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS40200D
Texas Instruments · DC-DC Converters · SOIC-8
TPS40200D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RC | input | Oscillator timing pin; connect resistor from VDD (≤750 μA maximum pull-down current) and capacitor to GND to set switching frequency over the 35-500 kHz range; can be synchronised by pulling below 150 mV for ≥20 ns via open-drain output; absolute maximum −0.3 V to 5.5 V. |
| 2 | SS | input | Soft-start programming pin; connect capacitor from SS to GND; internal pull-up resistance 65-170 kΩ; switching disabled when pulled below 150 mV (VSSRST reset threshold 100-200 mV); also serves as restart timer during hiccup overcurrent recovery; absolute maximum −0.3 V to 9.0 V. |
| 3 | COMP | output | Error amplifier output; connect control-loop Type-II compensation network between COMP and FB; source current 100-250 μA (VFB = 0.6 V, VCOMP = 1 V), sink current 1.0-2.5 mA (VFB = 1.2 V, VCOMP = 1 V); open-loop gain ≥60 dB, gain-bandwidth product 1.5-3 MHz; absolute maximum −0.3 V to 9.0 V. |
| 4 | FB | input | Error amplifier inverting input; regulation threshold 679-710 mV over −40°C to 125°C and 4.5-52 V VDD; input bias current 100-250 nA; connect centre-tap of output feedback resistor divider to this pin; absolute maximum −0.3 V to 5.5 V. |
| 5 | GND | power_in | Device ground reference; all internal voltages referenced to this pin; connect local bypass capacitor from VDD to GND. |
| 6 | GDRV | output | P-channel MOSFET gate driver output; gate drive voltage (VDD − VGDRV) = 6-10 V for VDD 12-52 V; pull-up source current 125-300 mA, pull-down sink current 200-300 mA; driver current folds back once gate is pulled to 8 V to limit dissipation at high input voltages; absolute maximum VIN − 10 V to VIN. |
| 7 | ISNS | input | Current-sense comparator input; connect a current-sense resistor between VDD and ISNS; overcurrent declared when voltage drop from VDD to ISNS exceeds 55-140 mV (VILIM, −40°C to 125°C, 4.5-52 V); absolute maximum −0.3 V to 52 V. |
| 8 | VDD | power_in | System input supply voltage; operating range 4.5-52 V; UVLO turn-on threshold 3.8-4.5 V with 110-275 mV hysteresis; quiescent current 1.5 mA typ / 3.0 mA max at fOSC = 300 kHz; connect local bypass capacitor from VDD to GND; absolute maximum −0.3 V to 52 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS40200D - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps40200d-etched.step/tps40200d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps40200d.step/tps40200d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
a3e23ec7367038ec, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).