component
MP9485GN-Z
Public Made by Adomby adom
MONOLITHIC POWER SYSTEMS (MPS) Global Sourcing Parts, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMP9485GN-Z
MONOLITHIC POWER SYSTEMS (MPS) · Global Sourcing Parts · SOIC-8-EP
MP9485GN-Z from MONOLITHIC POWER SYSTEMS (MPS), in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Feedback input to the voltage-feedback hysteretic comparator, which switches the power MOSFET at FB thresholds of 215mV (rising) and 185mV (falling) with FB input current limited to ±300nA. |
| 2 | NC | unconnected | No connection; the pin is not connected internally. |
| 3 | VIN | power_in | Input supply for the internal control circuitry, both BST regulators and the high-side switch, with a recommended supply range of 4.5V to 95V and a decoupling capacitor to be placed close to VIN. |
| 4 | BST | power_out | Positive supply for the internal floating high-side MOSFET driver, bypassed with a capacitor connected between BST and SW, with BST-to-SW limited to -0.3V to +6V. |
| 5 | SW | output | Output from the high-side switch node, which requires a low forward-voltage Schottky rectifier to ground placed close to SW, with the switch voltage rated -0.5V (-4V for under 10ns) to VIN + 0.5V. |
| 6 | DIM | input | PWM dimming input with a DIM up threshold of 0.8V to 1.5V (1.15V typical) that must be pulled below the threshold to turn dimming off and above it to turn dimming on, and which should be tied to EN when dimming is not needed. |
| 7 | EN | input | Positive-logic enable input with an EN up threshold of 1.4V to 1.7V (1.55V typical) that shuts the device down when pulled below threshold, and which enables the device when pulled above threshold or left floating (internal 2µA pull-up). |
| 8 | GND | power_in | Ground, to be placed as close to the output capacitor as possible to avoid the high-current switch paths, with the exposed pad connected to the GND plane for thermal performance. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MONOLITHIC POWER SYSTEMS (MPS) |
| Package | SOIC-8-EP |
| Category | Global Sourcing Parts |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN UVLO threshold | 3.6 | 4 | 4.4 | V | 4 | ||
| Shutdown supply current | 2 | 5 | µA | VEN = 0V | 4 | ||
| Quiescent supply current | 170 | 220 | µA | No load, VFB = 250mV | 4 | ||
| Upper switch leakage current | ISWLK | 0.01 | 1 | µA | VEN = 0V, VSW = 0V | 4 | |
| EN up threshold | VENH | 1.4 | 1.55 | 1.7 | V | 4 | |
| EN input current | IENI | 0.01 | 1 | µA | VEN = 5V | 4 | |
| EN sinking current | IENS | 2 | 3 | µA | VEN = 2V | 4 | |
| DIM up threshold | VDIMH | 0.8 | 1.15 | 1.5 | V | 4 | |
| DIM input current | IDIM | -1 | 1 | µA | VDIM = 5V or 0V | 4 | |
| FB voltage threshold high | VFBH | 209 | 215 | 221 | mV | 4.5V < VIN < 95V, VFB rising from 0V until VSW < 30V | 4 |
| FB voltage threshold low | VFBL | 179 | 185 | 191 | mV | 4.5V < VIN < 95V, VFB falling from 0.25V until VSW > 30V | 4 |
| FB input current | IFB | -300 | 300 | nA | VFB = 5V or 0V | 4 | |
| Supply voltage (VIN) | VIN | -0.3 | 100 | V | 3 | ||
| Switch voltage | VSW | -0.5 | V | -4V for <10ns; upper limit printed as VIN + 0.5V | 3 | ||
| BST to SW | -0.3 | 6 | V | 3 | |||
| All other pins | -0.3 | 6 | V | 3 | |||
| Junction temperature | 150 | °C | 3 | ||||
| Continuous power dissipation | 2.5 | W | TA = +25°C | 3 | |||
| Storage temperature | -65 | 150 | °C | 3 | |||
| Supply voltage (VIN) | VIN | 4.5 | 95 | V | 3 | ||
| EN and DIM voltages | 0 | 5 | V | 3 | |||
| Max switching frequency | 2 | MHz | 3 | ||||
| Operating junction temperature | -40 | 125 | °C | 3 | |||
| Thermal resistance junction-to-ambient | θJA | 50 | °C/W | SOIC-8 EP; measured on JESD51-7 4-layer board (note 4) | 3 | ||
| Thermal resistance junction-to-case | θJC | 10 | °C/W | SOIC-8 EP; measured on JESD51-7 4-layer board (note 4) | 3 |
CAD (KiCad official)
- Symbol:
MP9485GN-Z - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
mp9485gn-z-etched.step/mp9485gn-z-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mp9485gn-z.step/mp9485gn-z.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MONOLITHIC POWER SYSTEMS (MPS) datasheet (16 pp, sha256
514faab28c970cbf, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).