component
CD74HCT173M96
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HCT173M96
Texas Instruments · Flip Flops · SOIC-16
CD74HCT173M96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-low output enable 1; outputs go to high-impedance when either OE1 or OE2 is high, without affecting flip-flop operation. |
| 2 | OE2 | input | Active-low output enable 2; outputs go to high-impedance when either OE1 or OE2 is high, without affecting flip-flop operation. |
| 3 | Q0 | tri_state | Three-state buffered Q output of flip-flop 0, able to drive 15 LSTTL loads. |
| 4 | Q1 | tri_state | Three-state buffered Q output of flip-flop 1, able to drive 15 LSTTL loads. |
| 5 | Q2 | tri_state | Three-state buffered Q output of flip-flop 2, able to drive 15 LSTTL loads. |
| 6 | Q3 | tri_state | Three-state buffered Q output of flip-flop 3, able to drive 15 LSTTL loads. |
| 7 | CP | input | Shared clock input; Q outputs change on the positive-going (low-to-high) clock edge. |
| 8 | GND | power_in | Ground supply pin. |
| 9 | E1 | input | Data enable 1; when E1 or E2 is high, Q outputs are fed back and the flip-flops hold their state on the clock edge. |
| 10 | E2 | input | Data enable 2; when E1 or E2 is high, Q outputs are fed back and the flip-flops hold their state on the clock edge. |
| 11 | D3 | input | Data input to flip-flop 3, sampled on the rising clock edge. |
| 12 | D2 | input | Data input to flip-flop 2, sampled on the rising clock edge. |
| 13 | D1 | input | Data input to flip-flop 1, sampled on the rising clock edge. |
| 14 | D0 | input | Data input to flip-flop 0, sampled on the rising clock edge. |
| 15 | MR | input | Master reset input; taking MR to logic high resets the flip-flops (Q low). |
| 16 | VCC | power_in | Positive supply; 4.5 V to 5.5 V for HCT types, with a 0.1-µF bypass capacitor recommended close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD74HCT173M96 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
cd74hct173m96-etched.step/cd74hct173m96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hct173m96.step/cd74hct173m96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
6ad3dbf1cefe1afb, retrieved 2026-10-06, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).