RT6200GE
Public Made by Adomby adom
Richtek Tech DC-DC Converters, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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README
markdownRT6200GE
Richtek Tech · DC-DC Converters · SOT-23-6
RT6200GE from Richtek Tech, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_in | Bootstrap supply for the high-side gate driver. A capacitor between PHASE and BOOT forms a floating supply to drive the internal N-MOSFET gate above VIN. Absolute max BOOT voltage is VPHASE + 6V. |
| 2 | GND | power_in | Ground reference for the regulated output voltage. Must be routed carefully - kept out of the D1-to-C1 switching current path to prevent noise injection into the part. |
| 3 | FB | input | Feedback voltage input. An external resistor divider from VOUT to GND, tapped to FB, sets the output voltage against the internal 0.8V reference (VFB typ 0.8V, 0.784-0.816V). Divider values also set loop bandwidth. |
| 4 | EN | input | Enable control input (active high). Turns the converter on above ~1.2V (VIH typ 1.08V) and off below ~0.94V. If left open, an internal 1µA pull-up drives EN high; if pulling to VIN through a resistor, use ≥250kΩ. Absolute max 6V; recommended 0V to 5.5V. |
| 5 | VIN | power_in | Supply voltage input, 4.5V to 36V (absolute max 40V). Bypass VIN to GND with a suitable large ceramic capacitor near the pin to suppress input voltage spikes. |
| 6 | PHASE | output | Switch node - the drain of the internal high-side N-MOSFET and return for the bootstrap capacitor. Connects to the external inductor and catch (Schottky) diode. Absolute max −0.3V to (VIN + 0.3V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Richtek Tech |
| Package | SOT-23-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
RT6200GE
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Reference Voltage | VFB | 0.784 | 0.8 | 0.816 | V | 4.5V ≤ VIN ≤ 36V | 4 |
| Feedback Current | IFB | 0.1 | 0.3 | µA | VFB = 0.8V | 4 | |
| Oscillator Frequency | fSW | 1 | 1.2 | 1.4 | MHz | Duty < 90% | 4 |
| Under-Voltage Lockout Threshold Rising | 3.9 | 4.2 | 4.5 | V | 4 | ||
| EN Input Voltage Logic-High | VIH | 0.98 | 1.08 | 1.2 | V | 4 | |
| EN Input Voltage Logic-Low | VIL | 0.94 | 1 | 1.06 | V | 4 | |
| Switch Leakage Current | 10 | µA | VEN = 0V, VPHASE = 0V | 4 | |||
| Quiescent Current | IQ | 0.55 | 0.8 | mA | VEN = 2V, VFB = 1V (Not Switching) | 5 | |
| Switch On Resistance | RDS(ON) | 0.35 | Ω | VBOOT − VPHASE = 4.8V | 4 | ||
| Current Limit | ILIM | 1.2 | A | VBOOT − VPHASE = 4.8V, duty = 90% | 4 | ||
| Maximum Duty Cycle | 95 | % | 4 | ||||
| Minimum On-Time | tON | 80 | ns | 4 | |||
| Under-Voltage Lockout Threshold Hysteresis | 200 | mV | 4 | ||||
| EN Pull-Up Current | 1 | µA | VEN = 0V | 5 | |||
| Shutdown Current | ISHDN | 20 | µA | VEN = 0V | 5 | ||
| Thermal Shutdown | TSD | 150 | °C | 5 | |||
| Supply Voltage (absolute maximum) | VIN | 40 | V | 4 | |||
| PHASE Voltage (lower limit; upper limit VIN + 0.3V) | VPHASE | -0.3 | V | 4 | |||
| Other Pins Voltage | -0.3 | 6 | V | 4 | |||
| Power Dissipation (SOT-23-6) | PD | 0.48 | W | TA = 25°C | 4 | ||
| Package Thermal Resistance, junction to ambient (SOT-23-6) | θJA | 208.2 | °C/W | JEDEC 51-7 four-layer test board, TA = 25°C | 4 | ||
| Junction Temperature (absolute maximum) | TJ | 150 | °C | 4 | |||
| Lead Temperature (soldering) | 260 | °C | 10 sec soldering | 4 | |||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 4 | ||
| ESD Susceptibility HBM | 2 | kV | Human Body Model (Note 3) | 4 | |||
| ESD Susceptibility MM | 200 | V | Machine Model (Note 3) | 4 | |||
| Supply Voltage VIN (recommended) | VIN | 4.5 | 36 | V | 4 | ||
| Output Voltage VOUT (recommended) | VOUT | 0.8 | 15 | V | 4 | ||
| EN Voltage (recommended) | VEN | 0 | 5.5 | V | 4 | ||
| Junction Temperature Range (recommended) | TJ | -40 | 125 | °C | 4 | ||
| Ambient Temperature Range (recommended) | TA | -40 | 85 | °C | 4 |
CAD (KiCad official)
- Symbol:
RT6200GE - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
rt6200ge-etched.step/rt6200ge-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);rt6200ge.step/rt6200ge.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
rt6200ge.step |
97 KB | You want the bare part, or you mark your own boards. |
rt6200ge-etched.step |
1.9 MB | You want the part with RT6200GE already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 452 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Richtek Tech datasheet (12 pp, sha256
badee724273bb8fd, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).