component
a6211gljtr-t
Public Unreviewedby Ray
Allegro MicroSystems LLC LED Drivers, SOIC-8-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Allegro MicroSystems LLC · LED Drivers · SOIC-8-EP
A6211GLJTR-T from Allegro MicroSystems LLC, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Supply voltage input terminal. Operating range 6 to 48 V (absolute max −0.3 to 50 V). Bypass locally to GND. |
| 2 | TON | input | Regulator on-time setting resistor terminal. External resistor RON to VIN sets the buck switch on-time (and effective switching frequency). |
| 3 | EN | input | Logic input for Enable and PWM dimming. VIL = 0.4 V, VIH = 1.8 V (abs max −0.3 to VIN+0.3 V). Drive with 100 Hz to 2 kHz PWM for LED brightness control; low = low-power shutdown (~1 µA). |
| 4 | CS | input | Drive output current sense feedback. Connects to RSENSE between the LED cathode and GND; internal 0.2 V reference sets the average LED current (ILED = 0.2 V / RSENSE). Absolute max −0.3 to 7 V. |
| 5 | VCC | power_out | Internal linear regulator output (~5.3 V typ). Decouple with CVCC to GND. Absolute max VCC-to-GND −0.3 to 7 V; intended for internal use, not for external loading. |
| 6 | GND | power_in | Device ground terminal. Tie to the exposed thermal PAD and to the power ground plane. |
| 7 | BOOT | passive | DMOS gate-driver bootstrap terminal. External CBOOT capacitor between BOOT and SW provides the high-side gate drive supply. Absolute max −0.3 to VIN+8 V; UVLO ~2.9 V (BOOT-to-SW). |
| 8 | SW | output | Switched output terminal (source of the integrated high-side N-channel DMOS). Connects to the buck inductor L1 and to the freewheeling diode D1 cathode. Absolute max −1.5 to VIN+0.3 V; RDS(on) ≈ 0.25 Ω, 3 A max output. |
| PAD | PAD | power_in | Exposed pad on the underside of the package for enhanced thermal dissipation. Must be connected to GND (pin 6) and to a copper thermal pour. RθJP ≈ 2 °C/W. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Allegro MicroSystems LLC |
| Package | SOIC-8-EP |
| Category | LED-drv |
| Pins | 9 |
Ordering variants
A6211GLJTR-T
CAD (KiCad official)
- Symbol:
A6211GLJTR-T - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Allegro MicroSystems LLC datasheet (None pp, sha256
48373dd80f837b74, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).