component
SN74HC174PWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC174PWR
Texas Instruments · Flip Flops · TSSOP-16
SN74HC174PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low direct clear input, common to all six flip-flops; when CLR is low the outputs are forced low regardless of the D or CLK inputs. |
| 2 | 1Q | output | Output of flip-flop 1, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 3 | 1D | input | Data input to flip-flop 1, transferred to the Q1 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 4 | 2D | input | Data input to flip-flop 2, transferred to the Q2 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 5 | 2Q | output | Output of flip-flop 2, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 6 | 3D | input | Data input to flip-flop 3, transferred to the Q3 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 7 | 3Q | output | Output of flip-flop 3, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 8 | GND | power_in | Ground/common supply return for the device. |
| 9 | CLK | input | Common positive-edge-triggered clock input for all six flip-flops; data at D inputs meeting setup time is transferred to the outputs on the CLK low-to-high transition. |
| 10 | 4Q | output | Output of flip-flop 4, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 11 | 4D | input | Data input to flip-flop 4, transferred to the Q4 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 12 | 5Q | output | Output of flip-flop 5, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 13 | 5D | input | Data input to flip-flop 5, transferred to the Q5 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 14 | 6D | input | Data input to flip-flop 6, transferred to the Q6 output on the positive-going edge of CLK when CLR is high, with max input current of 1 µA. |
| 15 | 6Q | output | Output of flip-flop 6, capable of ±4-mA output drive at VCC=5 V (IOH=-4mA, IOL=4mA) and driving up to 10 LSTTL loads. |
| 16 | VCC | power_in | Positive supply voltage, recommended operating range 2 V to 6 V (typical 5 V), with a 0.1-µF bypass capacitor recommended as close to this pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
SN74HC174PWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
sn74hc174pwr-etched.step/sn74hc174pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc174pwr.step/sn74hc174pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
9b979c6ba2b4b122, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-5(text+vision), consensusclaude-opus-4-8(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).