TLE7269G from Infineon Technologies, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RxD1	output	Receive data output 1 is LOW in the dominant state and goes active LOW after a Wake-Up event at BUS1 or WK pin.
2	EN	input	Enable input with integrated pull-down; the device is set to normal operation mode when HIGH.
3	WK	input	Wake input is active LOW, negative edge triggered, with an internal pull-up.
4	TxD1	input	Transmit data input 1 has an integrated pull-down, is LOW in the dominant state, and goes active LOW after Wake-Up via the WK pin.
5	TxD2	input	Transmit data input 2 has an integrated pull-down and is LOW in the dominant state.
6	VIO	power_in	Logic voltage supply input for the RxD and TxD pins, supplied at 3.3 V or 5 V.
7	RxD2	output	Receive data output 2 is LOW in the dominant state and goes active LOW after a Wake-Up event at BUS2.
8	INH2	output	Inhibit output 2 is battery-supply related and HIGH (VS) in Normal and Stand-By operation mode, used to control an external voltage regulator or a master bus termination resistor.
9	W2O	input	Wake BUS 2 OFF switches off the Wake-Up feature on BUS 2 when active HIGH, and has an integrated pull-down.
10	BUS2	bidirectional	Bus 2 LIN bus line input/output with internal termination and pull-up current source, LOW in the dominant state.
11	GND	power_in	Ground connection.
12	BUS1	bidirectional	Bus 1 LIN bus line input/output with internal termination and pull-up current source, LOW in the dominant state.
13	VS	power_in	Battery supply input for the device.
14	INH1	output	Inhibit output 1 is battery-supply related and HIGH (VS) in Normal and Stand-By operation mode, used to control an external voltage regulator or a master bus termination resistor.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	SOIC-14
Category	Interface ICs
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Battery supply voltage	VS	-0.3		40	V	LIN Spec 2.1 Param. 10	19
Logic supply voltage	VIO	-0.3		5.5	V		19
Bus and WK input voltage versus GND	VBUS,G	-40		40	V		19
Bus and WK input voltage versus VS	VBUS,Vs	-40		40	V		19
Logic voltages at EN, W2O, TxD1, TxD2, RxD1, RxD2	Vlogic	-0.3		5.5	V		19
INH1, INH2 voltage versus GND	VINH,G	-0.3		40	V		19
INH1, INH2 voltage versus VS	VINH,Vs	-40		0.3	V		19
Output current at INH1, INH2	IINH	-150		80	mA	Output current internally limited to -150 mA (footnote 2)	19
Junction temperature	Tj	-40		150	°C		19
Storage temperature	Ts	-55		150	°C		19
Electrostatic discharge voltage at VS, BUS1, BUS2, WK versus GND	VESD	-6		6	kV	Human Body Model (100pF via 1.5 kΩ)	19
Electrostatic discharge voltage W2O versus VS	VESD	-1		1	kV	Human Body Model (100pF via 1.5 kΩ)	19
Electrostatic discharge voltage all pins except W2O versus VS	VESD	-2		2	kV	Human Body Model (100pF via 1.5 kΩ)	19
Supply Voltage Range for Normal Operation	VS(nor)	7		27	V	LIN Spec 2.1 Param. 10	20
Extended Supply Voltage range for operation	VS(ext)	5		40	V	Parameter deviations possible	20
Supply voltage VIO	VIO	3		5.5	V		20
Junction temperature (operating range)	Tj	-40		150	°C	Not subject to production test, specified by design (footnote 1)	20
Junction to Soldering Point	RthJSP			25	K/W	measured to pin 11	20
Junction to Ambient	RthJA		130		K/W	JESD 51-2, 51-3, FRA4 76,2 mm x 114,3 mm x 1,5 mm, 70 μm Cu, minimal footprint, Ta = 27°C	20
Thermal shutdown junction temperature	TjSD	150	170	190	°C		20
Current consumption at VS (both channels recessive)	IS,rec	0.5	1.6	3	mA	recessive state, without RL; VS = 13.5 V; VTxD = Vio	21
Current consumption normal mode at Vio	IVIO,norm		10	50	µA	Normal Operation mode. VIO=5 V	21
Current consumption at VS (both channels dominant)	IS,dom		3	5	mA	dominant state, without RL; VS = 13.5 V; VTxD = 0 V	21
Current consumption in sleep mode at Vio	IVIO,Sleep		1	10	µA	Sleep mode, VIO=5 V	21
Current consumption in sleep mode	IS,Sleep		7	12	µA	Sleep mode, VS = 18 V; VBUS= VWK = VS;	21
Current consumption in sleep mode (Tj < 85 °C)	IS,Sleep,typ		5	10	µA	Sleep mode, Tj < 85 °C; VS = 13.5 V; VWK= VS= VBUS;	21
Blocking under voltage detection at VS (VS on the falling edge)	Vs,UV,BLK	3.5		5	V	Communication blocked, no reset (see Figure 11)	21
Power ON under voltage detection at VS	Vs,UV,PON			3.5	V	Device reset to Stand-By Mode (see Figure 11)	21
Under voltage detection at VIO	VIO,UV	1.5	2.5	3	V	Communication blocked, no reset (see Figure 11)	21
HIGH level output current (RxD)	IRD,H	-10	-4	-2	mA	VRD = 0.8 × VIO	21
LOW level output current (RxD)	IRD,L	2	4	10	mA	VRD = 0.2 × VIO	21
LOW level input voltage range (TxD)	VTD,L	0			V	Dominant state	22
Pull-down resistance (TxD)	RTD	100	350	800	kΩ	VTxD = Vio	22
Low level leakage current (TxD)	ITD		0	10	µA	VEN = 0 V; VTxD = 0 V	22
Dominant current standby mode after Wake-Up	ITD,L	1.5	3	10	mA	VTxD = 0.9 V; WK = 0 V; VS = 13.5 V. Only valid for TxD 1	22
LOW level input voltage range (W2O)	VW2O,L	0			V		22
Pull-down resistance (W2O)	RW2O	15	35	60	kΩ		22
HIGH level input voltage range (EN)	VEN,on	2			V	Normal Operation Mode	22
LOW level input voltage range (EN)	VEN,off	0		0.8	V	Sleep Mode or Stand-By Mode	22
Pull-down resistance (EN)	REN	15	30	60	kΩ		22
Inhibit Ron resistance	RINH,on	22	36	50	Ω	IINH = -15 mA	22
Maximum INH output current	IINH	-150		-40	mA	VINH = 0 V	22
Leakage current INH	IINH,lk	-5		5	µA	Sleep Mode; VINH = 0 V	22
LOW level input voltage (WK)	VWK,L	-0.3			V	VS = 13.5 V;	23
Pull-up current (WK)	IWK,PU	-60	-30	-3	µA	VWK = 0V	23
High level leakage current (WK)	IWK,H,leak	-5		5	µA	VS = 0 V; VWK = 40 V	23
Dominant time for wake-up	tWK	30		150	µs		23
Dominant time for bus wake-up	tWK,bus	30		150	µs		23
Bus dominant output voltage maximum load (6.0 V ≤ VS ≤ 7.3 V)	VBUS,do			1.2	V	VTxD = 0 V; RL = 500 Ω; 6,0 ≤ VS ≤ 7,3 V	23
Bus dominant output voltage maximum load (10 < VS ≤ 18 V)	VBUS,do			2	V	VTxD = 0 V; RL = 500 Ω; 10 < VS ≤ 18 V	23
Bus short circuit current	IBUS_LIM	40	100	150	mA	VBUS = 13.5 V; LIN Spec 2.1 (Par. 12)	23
Leakage current (no GND)	IBUS_NO_GND	-1000	-450		µA	VS = 0 V; VBUS = -12 V; LIN Spec 2.1 (Par. 15)	23
Leakage current (dominant, passive)	IBUS_PAS_dom	-1			mA	VS = 18 V; VBUS = 0 V; LIN Spec 2.1 (Par. 13)	24
Leakage current (recessive, passive)	IBUS_PAS_rec			20	µA	VS = 8 V; VBUS = 18 V; LIN Spec 2.1 (Par. 14)	24
Bus pull-up resistance	Rslave	20	30	47	kΩ	Normal mode LIN Spec 2.1 (Par. 26)	24
LIN output current	IBUS	-60	-30	-5	µA	Sleep mode VS = 13.5 V; VEN = 0 V	24
Propagation delay LIN bus to RxD, dominant to RxD low	trx_pdf		1	6	µs	LIN Spec 2.1 (Par. 31); Vio = 5 V; CRxD = 20 pF	24
Propagation delay LIN bus to RxD, recessive to RxD high	trx_pdr		1	6	µs	LIN Spec 2.1 (Par. 31); Vio = 5 V; CRxD = 20 pF	24
Receiver delay symmetry	trx_sym	-2		2	µs	trx_sym = trx_pdf- trx_pdr; LIN Spec 2.1 (Par. 32); Vio = 5 V; CRxD = 20 pF	24
Delay time for mode change	tMODE			120	µs	See Figure 5, Figure 6	24

CAD (KiCad official)

Symbol: TLE7269G
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: tle7269g-etched.step / tle7269g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tle7269g.step / tle7269g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (34 pp, sha256 6a2e1bf338eb4601, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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TLE7269G

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