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TPS57060QDGQRQ1
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Texas Instruments DC-DC Converters, HVSSOP-10-EP-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS57060QDGQRQ1
Texas Instruments · DC-DC Converters · HVSSOP-10-EP-0.5mm
TPS57060QDGQRQ1 from Texas Instruments, in a HVSSOP-10-EP-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | A bootstrap capacitor is required between BOOT and PH; if its voltage falls below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. |
| 2 | VIN | power_in | Input supply voltage, 3.5 V to 60 V. |
| 3 | EN | input | Enable pin with an internal pullup current source; pull below 1.2 V to disable and float to enable, and adjust the input undervoltage lockout with two resistors. |
| 4 | SS/TR | input | Slow-start and tracking pin; an external capacitor sets the output rise time, and because this pin overrides the internal reference it can be used for tracking and sequencing. |
| 5 | RT/CLK | input | Resistor timing and external clock pin; an external resistor to ground sets the switching frequency, and pulling the pin above the PLL upper threshold converts it to a synchronization input. |
| 6 | PWRGD | output | Open-drain output that asserts low if the output voltage is low due to thermal shutdown, dropout, overvoltage or EN shutdown. |
| 7 | VSENSE | input | Inverting node of the transconductance (gm) error amplifier. |
| 8 | COMP | output | Error amplifier output and input to the output switch current comparator; frequency compensation components connect to this pin. |
| 9 | GND | power_in | Ground. |
| 10 | PH | output | The source of the internal high-side power MOSFET. |
| 11 | PowerPAD | power_in | GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-10-EP-0.5mm |
| Category | Power Management (PMIC) |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| PH DC voltage | PH | -0.6 | 65 | V | DC voltage | 4 | |
| Input voltage | VIN | -0.3 | 65 | V | 4 | ||
| EN voltage | EN | -0.3 | 5 | V | 4 | ||
| BOOT voltage | BOOT | 73 | V | 4 | |||
| VSENSE voltage | VSENSE | -0.3 | 3 | V | 4 | ||
| COMP voltage | COMP | -0.3 | 3 | V | 4 | ||
| PWRGD voltage | PWRGD | -0.3 | 6 | V | 4 | ||
| SS/TR voltage | SS/TR | -0.3 | 3 | V | 4 | ||
| RT/CLK voltage | RT/CLK | -0.3 | 3.6 | V | 4 | ||
| Operating junction temperature | -40 | 150 | °C | 4 | |||
| VIN supply voltage | VIN | 3.5 | 60 | V | 4 | ||
| Effective input capacitance | 3 | µF | 4 | ||||
| Operating ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Operating input voltage | VIN | 3.5 | 60 | V | 5 | ||
| Internal undervoltage lockout threshold | 2.5 | V | No voltage hysteresis, rising and falling | 5 | |||
| Shutdown supply current | 1.3 | 4 | μA | EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V | 5 | ||
| Shutdown supply current | 1.9 | 6.5 | μA | EN = 0 V, 125°C, 3.5 V ≤ VIN ≤ 60 V | 5 | ||
| Operating nonswitching supply current | 116 | 136 | μA | VSENSE = 0.83 V, VIN = 12 V, 25°C | 5 | ||
| Enable threshold voltage | 1.15 | 1.25 | 1.36 | V | No voltage hysteresis, rising and falling, 25°C | 5 | |
| Input current at enable threshold +50 mV | -3.8 | μA | Enable threshold +50 mV | 5 | |||
| Input current at enable threshold -50 mV | -0.9 | μA | Enable threshold -50 mV | 5 | |||
| Hysteresis current | -2.9 | μA | 5 | ||||
| Voltage reference | Vref | 0.792 | 0.8 | 0.808 | V | 5 | |
| High-side MOSFET on-resistance | 300 | mΩ | VIN = 3.5 V, BOOT-PH = 3 V | 5 | |||
| High-side MOSFET on-resistance | 200 | 410 | mΩ | VIN = 12 V, BOOT-PH = 6 V | 5 | ||
| Error amplifier input current | 50 | nA | 5 | ||||
| Error amplifier transconductance (gM) | gM | 97 | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V | 5 | ||
| Error amplifier transconductance (gM) during slow start | gM | 26 | μMhos | -2 μA < ICOMP < 2 μA, VCOMP = 1 V, VVSENSE = 0.4 V | 5 | ||
| Error amplifier dc gain | 10000 | V/V | VVSENSE = 0.8 V | 5 | |||
| Error amplifier bandwidth | 2700 | kHz | 5 | ||||
| Error amplifier source/sink | -7 | 7 | μA | V(COMP) = 1 V, 100 mV overdrive | 5 | ||
| COMP to switch current transconductance | 1.9 | A/V | 5 | ||||
| Current limit threshold | 0.6 | 0.94 | A | VIN = 12 V, TJ = 25°C | 6 | ||
| Thermal shutdown | 182 | °C | 6 | ||||
| Switching frequency using RT mode | fSW | 100 | 2500 | kHz | VIN = 12 V | 6 | |
| Switching frequency | fSW | 450 | 581 | 720 | kHz | VIN = 12 V, RT = 200 kΩ | 6 |
| Switching frequency using CLK mode | fSW | 300 | 2200 | kHz | VIN = 12 V | 6 | |
| Minimum CLK input pulse width | 40 | ns | 6 | ||||
| RT/CLK high threshold | 1.9 | 2.2 | V | VIN = 12 V | 6 | ||
| RT/CLK low threshold | 0.45 | 0.7 | V | VIN = 12 V | 6 | ||
| RT/CLK falling edge to PH rising edge delay | 60 | ns | Measured at 500 kHz with RT resistor in series | 6 | |||
| PLL lock in time | 100 | μs | Measured at 500 kHz | 6 | |||
| SS/TR charge current | 2 | μA | VSS/TR = 0.4 V | 6 | |||
| SS/TR-to-VSENSE matching | 45 | mV | VSS/TR = 0.4 V | 6 | |||
| SS/TR-to-reference crossover | 1 | V | 98% nominal | 6 | |||
| SS/TR discharge current (overload) | 112 | μA | VSENSE = 0 V, V(SS/TR) = 0.4 V | 6 | |||
| SS/TR discharge voltage | 54 | mV | VSENSE = 0 V | 6 | |||
| PWRGD threshold, VSENSE falling (fault) | PWRGDTH | 92 | % of VSENSE | VSENSE falling (fault) | 6 | ||
| PWRGD threshold, VSENSE rising (good) | PWRGDTH | 94 | % of VSENSE | VSENSE rising (good) | 6 | ||
| PWRGD threshold, VSENSE rising (fault) | PWRGDTH | 109 | % of VSENSE | VSENSE rising (fault) | 6 | ||
| PWRGD threshold, VSENSE falling (good) | PWRGDTH | 107 | % of VSENSE | VSENSE falling (good) | 6 | ||
| PWRGD threshold hysteresis | 2 | % of VSENSE | VSENSE falling and rising | 6 | |||
| PWRGD output high leakage | 10 | nA | VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C | 6 | |||
| PWRGD on resistance | 50 | Ω | I(PWRGD) = 3 mA, VSENSE < 0.79 V | 6 | |||
| Minimum VIN for defined PWRGD output | 0.95 | 1.5 | V | V(PWRGD) < 0.5 V, II(PWRGD) = 100 μA | 6 | ||
| Junction-to-ambient thermal resistance (DGQ) | RθJA | 67.4 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (DGQ) | RθJC(top) | 46.7 | °C/W | 5 | |||
| Junction-to-board thermal resistance (DGQ) | RθJB | 38.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter (DGQ) | ψJT | 1.9 | °C/W | 5 | |||
| Junction-to-board characterization parameter (DGQ) | ψJB | 38.1 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance (DGQ) | RθJC(bot) | 15.9 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
TPS57060QDGQRQ1 - Footprint:
Package_SO:MSOP-10-1EP_3x3mm_P0.5mm_EP1.68x1.88mm - 3D model: HVSSOP-10-EP-0.5mm (KiCad packages3D, STEP)
- 3D model files:
tps57060qdgqrq1-etched.step/tps57060qdgqrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps57060qdgqrq1.step/tps57060qdgqrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
5d7ad0bfe001428e, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).