component
DMC4050SSD-13-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDMC4050SSD-13-VB
VBsemi Elec · MOSFETs · SO-8
DMC4050SSD-13-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of MOSFET channel 1; the absolute maximum ratings apply, with VGS limited to ±20 V. |
| 2 | G1 | input | Gate terminal of MOSFET channel 1, with VGS limited to ±20 V per the absolute maximum ratings. |
| 3 | S2 | passive | Source terminal of MOSFET channel 2; the absolute maximum ratings apply, with VGS limited to ±20 V. |
| 4 | G2 | input | Gate terminal of MOSFET channel 2, with VGS limited to ±20 V per the absolute maximum ratings. |
| 5 | D2 | passive | Drain terminal of MOSFET channel 2, sharing the channel 2 drain with pin 6. |
| 6 | D2 | passive | Drain terminal of MOSFET channel 2, sharing the channel 2 drain with pin 5. |
| 7 | D1 | passive | Drain terminal of MOSFET channel 1, sharing the channel 1 drain with pin 8. |
| 8 | D1 | passive | Drain terminal of MOSFET channel 1, sharing the channel 1 drain with pin 7. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | SO-8 |
| Category | Triode/MOS Tube/Transistor |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage (N-Ch) | VDS | 40 | V | 1 | |||
| Drain-Source Voltage (P-Ch) | VDS | -40 | V | 1 | |||
| Gate-Source Voltage (N-Ch) | VGS | -20 | 20 | V | 1 | ||
| Gate-Source Voltage (P-Ch) | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current (N-Ch) | ID | 7.6 | A | TC = 70 °C, TJ = 150 °C | 1 | ||
| Continuous Drain Current (P-Ch) | ID | -6.8 | A | TC = 70 °C, TJ = 150 °C | 1 | ||
| Continuous Source-Drain Diode Current (N-Ch) | IS | 3.6 | A | TC = 25 °C | 1 | ||
| Continuous Source-Drain Diode Current (P-Ch) | IS | -3.6 | A | TC = 25 °C | 1 | ||
| Continuous Source-Drain Diode Current (N-Ch) | IS | 1.6 | A | TA = 25 °C | 1 | ||
| Continuous Source-Drain Diode Current (P-Ch) | IS | -1.6 | A | TA = 25 °C | 1 | ||
| Single Pulse Avalanche Current (N-Ch) | IAS | 20 | A | L = 0.1 mH | 1 | ||
| Single Pulse Avalanche Current (P-Ch) | IAS | -20 | A | L = 0.1 mH | 1 | ||
| Maximum Power Dissipation (N-Ch) | PD | 6.1 | W | TC = 25 °C | 1 | ||
| Maximum Power Dissipation (P-Ch) | PD | 5.2 | W | TC = 25 °C | 1 | ||
| Maximum Power Dissipation (N-Ch) | PD | 3 | W | TA = 25 °C | 1 | ||
| Maximum Power Dissipation (P-Ch) | PD | 3 | W | TA = 25 °C | 1 | ||
| Maximum Power Dissipation (N-Ch) | PD | 2.28 | W | TA = 70 °C | 1 | ||
| Maximum Power Dissipation (P-Ch) | PD | 2.28 | W | TA = 70 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Maximum Junction-to-Ambient (N-Ch) | RthJA | 20 | 32.5 | °C/W | t ≤ 10 s | 1 | |
| Maximum Junction-to-Ambient (P-Ch) | RthJA | 27 | 32.5 | °C/W | t ≤ 10 s | 1 | |
| Maximum Junction-to-Foot (Drain) (N-Ch) | RthJF | 10 | 20 | °C/W | Steady State | 1 | |
| Maximum Junction-to-Foot (Drain) (P-Ch) | RthJF | 19 | 28 | °C/W | Steady State | 1 | |
| Maximum Junction-to-Ambient steady state (N-Ch) | RthJA | 120 | °C/W | Steady state conditions (note d) | 1 | ||
| Maximum Junction-to-Ambient steady state (P-Ch) | RthJA | 110 | °C/W | Steady state conditions (note d) | 1 | ||
| Gate Threshold Voltage (N-Ch) | VGS(th) | 1 | 2.2 | V | VDS = VGS, ID = 250 µA | 2 | |
| Gate Threshold Voltage (P-Ch) | VGS(th) | -0.9 | -2.5 | V | VDS = VGS, ID = -250 µA | 2 | |
| Gate-Body Leakage (N-Ch) | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ±20 V | 2 | |
| Gate-Body Leakage (P-Ch) | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ±20 V | 2 | |
| Drain-Source On-State Resistance (N-Ch) | RDS(on) | 0.015 | Ω | VGS = 10 V, ID = 6.8 A | 2 | ||
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | 0.017 | Ω | VGS = -10 V, ID = -8 A | 2 | ||
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | 0.019 | Ω | VGS = -8 V, ID = -6.5 A | 2 | ||
| Drain-Source On-State Resistance (N-Ch) | RDS(on) | 0.018 | Ω | VGS = 4.5 V, ID = 6.6 A | 2 | ||
| Drain-Source On-State Resistance (P-Ch) | RDS(on) | 0.022 | Ω | VGS = -4.5 V, ID = -5 A | 2 | ||
| Gate Resistance (N-Ch) | Rg | 0.3 | 1.3 | 2.6 | Ω | f = 1 MHz | 2 |
| Gate Resistance (P-Ch) | Rg | 1.3 | 6.4 | 12.8 | Ω | f = 1 MHz | 2 |
| Total Gate Charge (N-Ch) | Qg | 13.3 | 20 | nC | VDS = 20 V, VGS = 10 V, ID = 10 A | 2 | |
| Total Gate Charge (P-Ch) | Qg | 13 | 20 | nC | VDS = -20 V, VGS = -10 V, ID = -10 A | 2 | |
| Total Gate Charge (N-Ch) | Qg | 6.5 | 10 | nC | VDS = 20 V, VGS = 4.5 V, ID = 10 A | 2 | |
| Total Gate Charge (P-Ch) | Qg | 21.7 | 33 | nC | VDS = -20 V, VGS = -4.5 V, ID = -10 A | 2 | |
| Turn-On Delay Time (P-Ch) | td(on) | 10 | 20 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω | 3 | |
| Rise Time (P-Ch) | tr | 9 | 18 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω | 3 | |
| Turn-Off Delay Time (P-Ch) | td(off) | 50 | 90 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω | 3 | |
| Fall Time (P-Ch) | tf | 13 | 26 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω | 3 | |
| Turn-On Delay Time (P-Ch) | td(on) | 42 | 75 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Rise Time (P-Ch) | tr | 40 | 70 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Turn-Off Delay Time (P-Ch) | td(off) | 40 | 70 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Fall Time (P-Ch) | tf | 18 | 35 | ns | VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -4.5 V, Rg = 1 Ω | 3 | |
| Body Diode Voltage (N-Ch) | VSD | 0.81 | 1.2 | V | IS = 5.4 A | 3 | |
| Body Diode Voltage (P-Ch) | VSD | -0.77 | -1.2 | V | IS = -2 A | 3 | |
| Body Diode Reverse Recovery Time (P-Ch) | trr | 41 | 80 | ns | IF = -5 A, dI/dt = -100 A/µs, TJ = 25 °C | 3 | |
| Body Diode Reverse Recovery Charge (N-Ch) | Qrr | 10 | 20 | nC | 3 | ||
| Body Diode Reverse Recovery Charge (P-Ch) | Qrr | 32 | 65 | nC | 3 |
CAD (KiCad official)
- Symbol:
DMC4050SSD-13-VB - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
dmc4050ssd-13-vb-etched.step/dmc4050ssd-13-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);dmc4050ssd-13-vb.step/dmc4050ssd-13-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (14 pp, sha256
3ebc9a673e4226b1, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).