component
TLV62595DMQR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTLV62595DMQR
Texas Instruments · DC-DC Converters · VSON-6(1.5x1.5)
TLV62595DMQR from Texas Instruments, in a VSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Device enable pin; must be pulled high to enable the device, pulling low disables it, and it must not be left floating. |
| 2 | PG | output | Power-good open-drain output; the pullup resistor can be connected to voltages up to 5.5 V, and the pin can be left floating if unused. |
| 3 | FB | input | Feedback pin; for fixed output voltage versions it must be connected to the output. |
| 4 | GND | power_in | Ground pin. |
| 5 | SW | passive | Switch pin of the power stage. |
| 6 | VIN | power_in | Input voltage pin, operating range 2.5 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSON-6(1.5x1.5) |
| Category | Power Supply Chip |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback regulation voltage | VFB | 594 | 600 | 606 | mV | PWM mode, 2.5V ≤ VIN ≤ 5.5V, TJ = -40°C to 125°C | 5 |
| Undervoltage lockout threshold | VUVLO | 2.1 | 2.2 | 2.3 | V | VIN falling | 5 |
| High-side FET switch current limit, DC | ILIM | 4.8 | 5.6 | A | 5 | ||
| EN high-level threshold voltage | VIH | 1 | V | VIN = 2.5 V to 5.5 V | 5 | ||
| EN low-level threshold voltage | VIL | 0.4 | V | VIN = 2.5 V to 5.5 V | 5 | ||
| PG low-level output voltage | VPG,OL | 0.4 | V | Isink = 1 mA | 5 | ||
| Quiescent current | IQ | 10 | µA | EN = high, no load, device not switching | 5 | ||
| Shutdown current | ISD | 0.05 | µA | EN = low, TJ = -40℃ to 85℃ | 5 | ||
| UVLO hysteresis | 160 | mV | VIN rising | 5 | |||
| Thermal shutdown threshold | TJSD | 150 | °C | TJ rising | 5 | ||
| Thermal shutdown hysteresis | 20 | °C | TJ falling | 5 | |||
| Soft-start time | tSS | 1.75 | ms | Time from EN high to 95% of VOUT nominal | 5 | ||
| Power good lower threshold, rising | VPG | 96 | % | VPG rising, VFB referenced to VFB nominal | 5 | ||
| Power good lower threshold, falling | VPG | 92 | % | VPG falling, VFB referenced to VFB nominal | 5 | ||
| Power good upper threshold, rising | VPG | 105 | % | VPG rising, VFB referenced to VFB nominal | 5 | ||
| Power good upper threshold, falling | VPG | 110 | % | VPG falling, VFB referenced to VFB nominal | 5 | ||
| PG input leakage current | IPG,LKG | 0.01 | µA | VPG = 5.0 V | 5 | ||
| PG deglitch delay, rising edge | tPG,DLY | 100 | µs | PG rising edge | 5 | ||
| PG deglitch delay, falling edge | tPG,DLY | 20 | µs | PG falling edge | 5 | ||
| Feedback input leakage current | IFB,LKG | 0.01 | µA | VFB = 0.6V | 5 | ||
| Output discharge current | IDIS | 400 | mA | VSW = 0.4V; EN = low | 5 | ||
| Load regulation | 0.1 | %/A | IOUT = 0.5A to 3A, VOUT = 1.8V | 5 | |||
| High-side FET on-resistance | RDS(on) | 26 | mΩ | 5 | |||
| Low-side FET on-resistance | RDS(on) | 25 | mΩ | 5 | |||
| PWM switching frequency | fSW | 2.2 | MHz | IOUT = 1A, VOUT = 1.8V | 5 | ||
| Pin voltage VIN, FB, EN, PG | -0.3 | 6 | V | 4 | |||
| Pin voltage SW (DC) | -0.3 | 0.3 | V | Max is VIN + 0.3 V | 4 | ||
| Pin voltage SW (DC, in current limit) | -1 | 0.3 | V | Max is VIN + 0.3 V | 4 | ||
| Pin voltage SW (AC, less than 10ns) | -2.5 | 10 | V | While switching | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human body model, ANSI/ESDA/JEDEC JS-001 | 4 | |
| ESD CDM | V(ESD) | -500 | 500 | V | Charged device model, JS-002 | 4 | |
| Input voltage range | VIN | 2.5 | 5.5 | V | 4 | ||
| Output voltage range | VOUT | 0.6 | 4 | V | 4 | ||
| Output current range | IOUT | 0 | 4 | A | 4 | ||
| PG pull-up resistor voltage | VPG | 5.5 | V | 4 | |||
| Sink current at PG pin | ISINK_PG | 1 | mA | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 129.5 | °C/W | DMQ (JEDEC), 6 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 103.9 | °C/W | DMQ (JEDEC) | 4 | ||
| Junction-to-board thermal resistance | RθJB | 33.1 | °C/W | DMQ (JEDEC) | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 3.8 | °C/W | DMQ (JEDEC) | 4 | ||
| Junction-to-board characterization parameter | YJB | 33.1 | °C/W | DMQ (JEDEC) | 4 |
CAD (KiCad official)
- Symbol:
TLV62595DMQR - Footprint:
Package_SON:WSON-6_1.5x1.5mm_P0.5mm - 3D model: VSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files:
tlv62595dmqr-etched.step/tlv62595dmqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv62595dmqr.step/tlv62595dmqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
90b6097fafbdf9d5, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).