component
TPS54427DDAR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS54427DDAR
Texas Instruments · DC-DC Converters · SOP-8
TPS54427DDAR from Texas Instruments, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | Enable input control. Active high; must be pulled up to enable the device. VIH ≥ 1.6 V, VIL ≤ 0.6 V. Internal ~450 kΩ pull-down to GND (225-900 kΩ). Absolute max −0.3 to 20 V. |
| 2 | VFB | input | Converter feedback input. Connect to the output voltage via a resistor divider to set VOUT. Internal reference (VFBTH) is 765 mV typ (757-773 mV at 25 °C). Input current ±0.1 µA max. |
| 3 | VREG5 | power_out | 5.5 V internal LDO power supply output (5.2-5.7 V, up to 60 mA). Bypass with a ~1 µF capacitor to GND. Not active when EN is low. Also feeds internal gate drive. |
| 4 | SS | input | Soft-start control. Connect an external capacitor from SS to GND to program the soft-start ramp time. Absolute max −0.3 to 6.5 V. |
| 5 | GND | power_in | Ground pin. Power ground return for the switching circuit. Sensitive SS and VFB returns must be tied to GND at a single point. |
| 6 | SW | power_out | Switch node between the high-side NFET (drain of low-side, source of high-side). Connect to the output inductor. Absolute max −2 to 20 V (−3 to 22 V for 10 ns transients). |
| 7 | VBST | power_in | Bootstrap supply for the high-side FET gate driver. Connect a 0.1 µF capacitor between VBST and SW. An internal diode is connected between VREG5 and VBST for charging. VBST(vs SW) max 6 V. |
| 8 | VIN | power_in | Input voltage supply pin. Operating range 4.5 V to 18 V (absolute max 20 V). Bypass with ceramic capacitance close to the pin. |
| 9 | PowerPAD | power_in | Exposed thermal pad on the underside. Must be soldered to the PCB ground plane for proper thermal dissipation and must be electrically connected to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOP-8 |
| Category | PMIC |
| Pins | 9 |
Ordering variants
Same part, different packaging or reel option.
TPS54427DDARTPS54427DDARDRCTPS54427DDARDRCR
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage (VIN, EN) | VIN, EN | -0.3 | 20 | V | 4 | ||
| Input voltage VBST | VBST | -0.3 | 26 | V | 4 | ||
| Input voltage VBST (10 ns transient) | VBST | -0.3 | 28 | V | 10 ns transient | 4 | |
| Input voltage VBST (vs SW) | VBST (vs SW) | -0.3 | 6.5 | V | 4 | ||
| Input voltage VFB, SS | VFB, SS | -0.3 | 6.5 | V | 4 | ||
| Input voltage SW | SW | -2 | 20 | V | 4 | ||
| Input voltage SW (10 ns transient) | SW | -3 | 22 | V | 10 ns transient | 4 | |
| Output voltage VREG5 | VREG5 | -0.3 | 6.5 | V | 4 | ||
| Voltage GND | GND | -0.3 | 0.3 | V | 4 | ||
| Voltage from GND to thermal pad | Vdiff | -0.2 | 0.2 | V | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 4 | ||
| VIN supply input voltage | VIN | 4.5 | 18 | V | 4 | ||
| Input voltage VBST | VBST | -0.1 | 24 | V | 4 | ||
| Input voltage VBST (10 ns transient) | VBST | -0.1 | 27 | V | 10 ns transient | 4 | |
| Input voltage VBST (vs SW) | VBST(vs SW) | -0.1 | 6 | V | 4 | ||
| Input voltage SS | SS | -0.1 | 5.7 | V | 4 | ||
| Input voltage EN | EN | -0.1 | 18 | V | 4 | ||
| Input voltage VFB | VFB | -0.1 | 5.5 | V | 4 | ||
| Input voltage SW | SW | -1.8 | 18 | V | 4 | ||
| Input voltage SW (10 ns transient) | SW | -3 | 21 | V | 10 ns transient | 4 | |
| Input voltage GND | GND | -0.1 | 0.1 | V | 4 | ||
| Output voltage VREG5 | VREG5 | -0.1 | 5.7 | V | 4 | ||
| Output current IVREG5 | IO | 0 | 10 | mA | IVREG5 | 4 | |
| Operating free-air temperature | TA | -40 | 85 | °C | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (DDA) | RθJA | 42.1 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (DDA) | RθJC(top) | 50.9 | °C/W | 5 | |||
| Junction-to-board thermal resistance (DDA) | RθJB | 31.8 | °C/W | 5 | |||
| Junction-to-board characterization parameter (DDA) | ψJB | 13.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance (DDA) | RθJC(bot) | 7.1 | °C/W | 5 | |||
| Operating non-switching supply current | IVIN | 950 | 1400 | μA | TA = 25°C, EN = 5 V, VFB = 0.8 V | 5 | |
| Shutdown supply current | IVINSDN | 3 | 10 | μA | TA = 25°C, EN = 0 V | 5 | |
| EN high-level input voltage | VENH | 1.6 | V | EN | 5 | ||
| EN low-level input voltage | VENL | 0.6 | V | EN | 5 | ||
| EN pin resistance to GND | REN | 225 | 450 | 900 | kΩ | VEN = 12 V | 5 |
| VFB threshold voltage | VFBTH | 757 | 765 | 773 | mV | TA = 25°C, VO = 1.05 V, continuous mode | 5 |
| VFB threshold voltage over temperature | VFBTH | 751 | 765 | 779 | mV | TA = -40°C to 85°C, VO = 1.05 V, continuous mode | 5 |
| VFB input current | IVFB | -0.1 | 0 | 0.1 | μA | VFB = 0.8 V, TA = 25°C | 5 |
| VREG5 output voltage | VVREG5 | 5.2 | 5.5 | 5.7 | V | TA = 25°C, 6.0 V < VIN < 18 V, 0 < IVREG5 < 5 mA | 5 |
| Line regulation | VLN5 | 25 | mV | 6 V < VIN < 18 V, IVREG5 = 5 mA | 5 | ||
| Load regulation | VLD5 | 100 | mV | 0 mA < IVREG5 < 5 mA | 5 | ||
| Output current | IVREG5 | 60 | mA | VIN = 6 V, VREG5 = 4.0 V, TA = 25°C | 5 | ||
| High side switch resistance (DDA) | RDS(on)h | 70 | mΩ | 25°C, VBST - SW = 5.5 V | 5 | ||
| Low side switch resistance | RDS(on)l | 53 | mΩ | 25°C | 5 | ||
| Current limit | Iocl | 4.6 | 5.3 | 6.8 | A | Lout = 1.5 µH | 5 |
| Thermal shutdown threshold | TSDN | 170 | °C | Shutdown temperature | 6 | ||
| Thermal shutdown hysteresis | TSDN | 35 | °C | Hysteresis | 6 | ||
| On time | tON | 150 | ns | VIN = 12 V, VO = 1.05 V | 6 | ||
| Minimum off time | tOFF(MIN) | 260 | 310 | ns | TA = 25°C, VFB = 0.7 V | 6 | |
| SS charge current | ISSC | 4.2 | 6 | 7.8 | μA | VSS = 1 V | 6 |
| SS discharge current | ISSD | 0.1 | 0.2 | mA | VSS = 0.5 V | 6 | |
| UVLO wake up VREG5 voltage | UVLO | 3.45 | 3.75 | 4.05 | V | Wake up VREG5 voltage | 6 |
| UVLO hysteresis VREG5 voltage | UVLO | 0.19 | 0.32 | 0.45 | V | Hysteresis VREG5 voltage | 6 |
CAD (KiCad official)
- Symbol:
TPS54427DDAR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
tps54427ddar-etched.step/tps54427ddar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps54427ddar.step/tps54427ddar.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps54427ddar.step |
123 KB | You want the bare part, or you mark your own boards. |
tps54427ddar-etched.step |
2.2 MB | You want the part with TPS54427DDAR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 558 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (32 pp, sha256
75b4634a9b5c2b51, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).