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PIC12F1840-E
Public Made by Adomby adom
Microchip Tech Microcontrollers (MCU/MPU/SOC), PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownPIC12F1840-E
Microchip Tech · Microcontrollers (MCU/MPU/SOC) · PDIP-8
PIC12F1840-E from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply; the PIC12F1840 operates from 2.3V-5.5V (the PIC12LF1840 from 1.8V-3.6V). |
| 2 | RA5 | bidirectional | General-purpose I/O (25 mA sink/source) that is also CLKIN external clock input, OSC1 crystal connection, Timer1 oscillator input T1OSI, Timer1 clock input T1CKI, SR latch inverting output SRNQ, PWM P1A, CCP1, and USART DT/RX. |
| 3 | RA4 | bidirectional | General-purpose I/O (25 mA sink/source) that is also ADC channel AN3, capacitive sensing CPS3, OSC2/CLKOUT crystal connection or FOSC/4 output, Timer1 oscillator output T1OSO, comparator C1IN1-, clock reference CLKR, SPI SDO, USART CK/TX, PWM P1B, Timer1 gate T1G, and modulator carrier input MDCIN2. |
| 4 | MCLR/VPP/RA3 | input | RA3 is an input-only pin (TRISA3 always reads '1') that functions as Master Clear reset input MCLR with internal pull-up or as high-voltage programming input VPP, and also carries the SS and T1G alternate functions. |
| 5 | RA2 | bidirectional | General-purpose I/O (25 mA sink/source) that is also ADC channel AN2, capacitive sensing CPS2, comparator C1OUT, SR latch output SRQ, Timer0 clock T0CKI, CCP1/P1A, ECCP auto-shutdown fault input FLT0, I2C SDA, SPI SDI, external interrupt INT, and modulator carrier input MDCIN1. |
| 6 | RA1/ICSPCLK | bidirectional | General-purpose I/O (25 mA sink/source) that is also ADC channel AN1, VREF input, capacitive sensing CPS1, comparator C1IN0-, SR latch input SRI, USART RX/DT, I2C SCL, SPI SCK, modulator source input MDMIN, and the ICSP serial programming clock ICSPCLK. |
| 7 | RA0/ICSPDAT | bidirectional | General-purpose I/O (25 mA sink/source) that is also ADC channel AN0, DAC output DACOUT, capacitive sensing CPS0, comparator C1IN+, USART TX/CK, SPI SDO and SS, PWM P1B, modulator output MDOUT, and the ICSP data pin ICSPDAT. |
| 8 | VSS | power_in | Ground reference for the device. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -40 | 125 | °C | 302 | |||
| Storage temperature | -65 | 150 | °C | 302 | |||
| Voltage on VDD with respect to VSS, PIC12F1840 | VDD | -0.3 | 6.5 | V | PIC12F1840 | 302 | |
| Voltage on MCLR with respect to VSS | -0.3 | 9 | V | 302 | |||
| Voltage on all other pins with respect to VSS | -0.3 | V | Printed maximum is (VDD + 0.3V) | 302 | |||
| Maximum current out of VSS pin, industrial | 170 | mA | -40°C ≤ TA ≤ +85°C for industrial | 302 | |||
| Maximum current out of VSS pin, extended | 70 | mA | -40°C ≤ TA ≤ +125°C for extended | 302 | |||
| Maximum current into VDD pin, industrial | 170 | mA | -40°C ≤ TA ≤ +85°C for industrial | 302 | |||
| Maximum current into VDD pin, extended | 70 | mA | -40°C ≤ TA ≤ +125°C for extended | 302 | |||
| Clamp current | IK | 20 | mA | VPIN < 0 or VPIN > VDD | 302 | ||
| Operating temperature, extended (-E) | TA | -40 | 125 | °C | Extended range, -40°C ≤ TA ≤ +125°C | 305 | |
| Supply voltage VDD (VDDMIN, VDDMAX) | VDD | 2.3 | 5.5 | V | FOSC ≤ 16 MHz | 305 | |
| Supply voltage VDD (VDDMIN, VDDMAX) | VDD | 2.5 | 5.5 | V | FOSC ≤ 32 MHz | 305 | |
| RAM data retention voltage | VDR | 1.7 | V | Device in Sleep mode | 305 | ||
| VDD rise rate to ensure internal Power-on Reset signal | SVDD | 0.05 | V/ms | See Section 7.1 Power-On Reset (POR) | 305 | ||
| Fixed Voltage Reference voltage for ADC | VADFVR | -8 | 6 | % | 1.024V, VDD ≥ 2.5V; 2.048V, VDD ≥ 2.5V; 4.096V, VDD ≥ 4.75V | 305 | |
| Fixed Voltage Reference voltage for Comparator and DAC | VCDAFVR | -11 | 7 | % | 1.024V, VDD ≥ 2.5V; 2.048V, VDD ≥ 2.5V; 4.096V, VDD ≥ 4.75V | 305 | |
| Supply current IDD, LP oscillator 32 kHz (extended) | IDD | 17 | 60 | µA | VDD = 2.3V, FOSC = 32 kHz LP oscillator, -40°C ≤ TA ≤ +125°C | 307 | |
| Supply current IDD, LP oscillator 32 kHz (extended) | IDD | 19 | 70 | µA | VDD = 3.0V, FOSC = 32 kHz LP oscillator, -40°C ≤ TA ≤ +125°C | 307 | |
| Supply current IDD, LP oscillator 32 kHz (extended) | IDD | 22 | 80 | µA | VDD = 5.0V, FOSC = 32 kHz LP oscillator, -40°C ≤ TA ≤ +125°C | 307 | |
| Supply current IDD, HFINTOSC 16 MHz | IDD | 0.9 | 1.5 | mA | VDD = 2.3V, FOSC = 16 MHz HFINTOSC | 308 | |
| Supply current IDD, HFINTOSC 16 MHz | IDD | 1.2 | 2 | mA | VDD = 3.0V, FOSC = 16 MHz HFINTOSC | 308 | |
| Supply current IDD, HFINTOSC 16 MHz | IDD | 1.3 | 2.1 | mA | VDD = 5.0V, FOSC = 16 MHz HFINTOSC | 308 | |
| Supply current IDD, EXTRC 4 MHz | IDD | 290 | 400 | µA | VDD = 2.3V, FOSC = 4 MHz EXTRC | 309 | |
| Supply current IDD, EXTRC 4 MHz | IDD | 415 | 550 | µA | VDD = 3.0V, FOSC = 4 MHz EXTRC | 309 | |
| Supply current IDD, EXTRC 4 MHz | IDD | 495 | 600 | µA | VDD = 5.0V, FOSC = 4 MHz EXTRC | 309 | |
| Power-down base current IPD (WDT, BOR, FVR, T1OSC disabled), +125°C | IPD | 0.2 | 10 | µA | VDD = 2.3V, all peripherals inactive, Max. at +125°C | 310 | |
| Power-down base current IPD (WDT, BOR, FVR, T1OSC disabled), +125°C | IPD | 0.3 | 12 | µA | VDD = 3.0V, all peripherals inactive, Max. at +125°C | 310 | |
| Power-down base current IPD (WDT, BOR, FVR, T1OSC disabled), +125°C | IPD | 0.5 | 15 | µA | VDD = 5.0V, all peripherals inactive, Max. at +125°C | 310 | |
| Input low voltage, I/O port with TTL buffer | VIL | 0.8 | V | 4.5V ≤ VDD ≤ 5.5V | 312 | ||
| Input high voltage, I/O port with TTL buffer | VIH | 2 | V | 4.5V ≤ VDD ≤ 5.5V | 312 | ||
| Input leakage current, I/O ports (85°C) | IIL | -125 | 5 | 125 | nA | VSS ≤ VPIN ≤ VDD, pin at high impedance, 85°C | 312 |
| Input leakage current, MCLR (85°C) | IIL | -200 | 50 | 200 | nA | VSS ≤ VPIN ≤ VDD, pin at high impedance, 85°C | 312 |
| Weak pull-up current | IPUR | 25 | 100 | 200 | µA | VDD = 3.3V, VPIN = VSS | 312 |
| Weak pull-up current | IPUR | 25 | 140 | 300 | µA | VDD = 5.0V, VPIN = VSS | 312 |
| Output low voltage, I/O ports | VOL | 0.6 | V | IOL = 8 mA, VDD = 5V | 312 | ||
| Capacitive loading, OSC2 pin | COSC2 | 15 | pF | In XT, HS and LP modes when external clock is used to drive OSC1 | 313 | ||
| Capacitive loading, all I/O pins | CIO | 50 | pF | All I/O pins | 313 | ||
| MCLR pulse width (low) | TMCL | 2 | µs | 321 | |||
| Low-power Watchdog Timer time-out period | TWDTLP | 10 | 16 | 27 | ms | VDD = 3.3V-5V, 1:16 Prescaler used | 321 |
| Power-up Timer period, PWRTE = 0 | TPWRT | 40 | 65 | 140 | ms | PWRTE = 0 | 321 |
| Brown-out Reset voltage, BORV = 0 | VBOR | 2.55 | 2.7 | 2.85 | V | BORV = 0, PIC12F1840 | 321 |
| Brown-out Reset voltage, BORV = 1 | VBOR | 2.35 | 2.45 | 2.58 | V | BORV = 1, PIC12F1840 | 321 |
| Brown-out Reset hysteresis | VHYST | 0 | 25 | 75 | mV | -40°C to +85°C | 321 |
| I/O high-impedance from MCLR Low or Watchdog Timer Reset | TIOZ | 2 | µs | 321 | |||
| Brown-out Reset DC response time | TBORDC | 1 | 3 | 35 | µs | VDD ≤ VBOR | 321 |
| Data EEPROM byte endurance | ED | 100 | K E/W | -40°C to +85°C | 314 | ||
| Program Flash cell endurance | EP | 10 | K E/W | -40°C to +85°C, self-write and block erase | 314 | ||
| HFINTOSC frequency tolerance | HFOSC | -2 | 2 | % | HFINTOSC, 0°C ≤ TA ≤ +60°C, VDD ≥ 2.5V | 318 | |
| HFINTOSC frequency tolerance | HFOSC | -3 | 3 | % | HFINTOSC, 60°C ≤ TA ≤ +85°C, VDD ≥ 2.5V | 318 | |
| HFINTOSC frequency tolerance | HFOSC | -5 | 5 | % | HFINTOSC, -40°C ≤ TA ≤ +125°C | 318 | |
| ADC clock period TAD (FOSC-based) | TAD | 1 | 9 | µs | VDD = 3.0V, TA ≤ 25°C | 324 | |
| Maximum junction temperature | TJMAX | 150 | °C | 315 | |||
| Thermal resistance junction to ambient, 8-pin PDIP | JA | 89.3 | °C/W | 8-pin PDIP package | 315 | ||
| Thermal resistance junction to case, 8-pin PDIP | JC | 43.1 | °C/W | 8-pin PDIP package | 315 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | SN = SOIC, 8-Lead Pattern: QTP, SQTP, Code or Special Requirements | 395 |
CAD (KiCad official)
- Symbol:
PIC12F1840-E - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files:
pic12f1840-e-etched.step/pic12f1840-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic12f1840-e.step/pic12f1840-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (397 pp, sha256
79e88d8e63728e96, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).