component
LM1881N
Public Made by Adomby adom
HGSEMI Interface - Specialized, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM1881N
HGSEMI · Interface - Specialized · DIP-8
LM1881N from HGSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | COMPOSITE SYNC OUTPUT | output | Composite sync output, a reproduction of the sync waveform with video removed; max output sink current 5 mA. |
| 2 | COMPOSITE VIDEO INPUT | input | AC-coupled composite video input via a 0.1 µF capacitor, clamped to 1.5 V DC at sync tip, accepting 0.5 V to 2 V p-p. |
| 3 | VERTICAL SYNC OUTPUT | output | Vertical sync output pulse; max output sink current 5 mA. |
| 4 | GND | power_in | Ground connection. |
| 5 | BURST/BACK PORCH OUTPUT | output | Burst gate/back porch pulse output, about 4 µs wide; max output sink current 5 mA. |
| 6 | RSET | passive | Connect the RSET resistor (680 kΩ typical) to ground, with a 0.1 µF decoupling capacitor, to set internal current levels; reference voltage 1.10 V to 1.35 V. |
| 7 | ODD/EVEN OUTPUT | output | Odd/even field index output, low during even field and high during odd field; max output sink current 2 mA. |
| 8 | VCC | power_in | Supply voltage 5 V to 12 V DC, with a decoupling capacitor; absolute maximum 13.2 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Current (outputs at logic 1) | 5.2 | 10 | mA | VCC = 5V; outputs at logic 1 | 3 | ||
| Supply Current (outputs at logic 1) | 5.5 | 12 | mA | VCC = 12V; outputs at logic 1 | 3 | ||
| DC Input Voltage | 1.3 | 1.5 | 1.8 | V | Pin 2 | 3 | |
| Input Threshold Voltage | 55 | 70 | 85 | mV | Note 6 | 3 | |
| Input Discharge Current | 6 | 11 | 16 | µA | Pin 2; VIN = 2V | 3 | |
| Input Clamp Charge Current | 0.2 | 0.8 | mA | Pin 2; VIN = 1V | 3 | ||
| RSET Pin Reference Voltage | 1.1 | 1.22 | 1.35 | V | Pin 6; Note 7 | 3 | |
| Composite Sync & Vertical Outputs Logic 1 voltage | 4 | 4.5 | V | IOUT = 40 µA; VCC = 5V | 3 | ||
| Composite Sync & Vertical Outputs Logic 1 voltage | 11 | V | IOUT = 40 µA; VCC = 12V | 3 | |||
| Composite Sync & Vertical Outputs Logic 1 voltage | 2.4 | 3.6 | V | IOUT = 1.6 mA; VCC = 5V | 3 | ||
| Composite Sync & Vertical Outputs Logic 1 voltage | 10 | V | IOUT = 1.6 mA; VCC = 12V | 3 | |||
| Burst Gate & Odd/Even Outputs Logic 1 voltage | 4 | 4.5 | V | IOUT = 40 µA; VCC = 5V | 3 | ||
| Burst Gate & Odd/Even Outputs Logic 1 voltage | 11 | V | IOUT = 40 µA; VCC = 12V | 3 | |||
| Composite Sync Output Logic 0 voltage | 0.2 | 0.8 | V | IOUT = −1.6 mA; Pin 1 | 3 | ||
| Vertical Sync Output Logic 0 voltage | 0.2 | 0.8 | V | IOUT = −1.6 mA; Pin 3 | 3 | ||
| Burst Gate Output Logic 0 voltage | 0.2 | 0.8 | V | IOUT = −1.6 mA; Pin 5 | 3 | ||
| Odd/Even Output Logic 0 voltage | 0.2 | 0.8 | V | IOUT = −1.6 mA; Pin 7 | 3 | ||
| Vertical Sync Width | 190 | 230 | 300 | µs | 3 | ||
| Burst Gate Width | 2.5 | 4 | 4.7 | µs | 2.7 kΩ from Pin 5 to VCC | 3 | |
| Vertical Default Time | 32 | 65 | 90 | µs | Note 8 | 3 | |
| Supply Voltage | 13.2 | V | 2 | ||||
| Input Voltage | 3 | Vp-p | VCC = 5V | 2 | |||
| Input Voltage | 6 | Vp-p | VCC = 8V | 2 | |||
| Output Sink Current | 5 | mA | Pins 1, 3, 5 | 2 | |||
| Output Sink Current | 2 | mA | Pin 7 | 2 | |||
| Package Dissipation | 1100 | mW | Note 2 | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| ESD Susceptibility (Human Body Model) | 2 | kV | Note 3; 100 pF through 1.5 kΩ | 2 | |||
| ESD Susceptibility (Machine Model) | 200 | V | Note 4; 220-240 pF through all pins | 2 | |||
| Soldering Temperature, Dual-In-Line Package | 260 | °C | 10 s | 2 | |||
| Lead Temperature (Soldering) | 260 | °C | 10 s | 2 | |||
| Maximum Junction Temperature | 150 | °C | Note 2 (derating basis) | 3 | |||
| Package Thermal Resistance, Junction to Ambient | 110 | °C/W | Note 2; derate above 25°C ambient | 3 | |||
| Supply Voltage (operating) | 5 | 12 | V | Single supply; Application Notes text | 5 | ||
| Composite Video Input Amplitude (operating) | 0.5 | 2 | Vp-p | Positive-polarity composite video; Application Notes text | 5 |
CAD (KiCad official)
- Symbol:
LM1881N - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
lm1881n-etched.step/lm1881n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm1881n.step/lm1881n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (17 pp, sha256
18a032033306f1df, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).