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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DP83620SQX

Texas Instruments · Ethernet Transceivers · WQFN-48-EP(7x7)

DP83620SQX from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TX_CLK	output	25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode with integrated 50 ohm termination.
2	TX_EN	input	MII Transmit Enable; active high input indicates presence of valid data on TXD[3:0] with internal pull-down.
3	TXD_0	input	MII Transmit Data input bit 0; accepts data synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
4	TXD_1	input	MII Transmit Data input bit 1; accepts data synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
5	TXD_2	input	MII Transmit Data input bit 2; accepts data synchronous to TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
6	TXD_3	input	MII Transmit Data input bit 3 with internal pull-down; accepts data synchronous to TX_CLK or RMII data on TXD[1].
7	PWRDOWN/INTN	input	Power Down input (default) or Interrupt output with internal pull-up; assert low to enable power down mode or signal interrupt when INT_OE bit is set.
8	TCK	input	Test Clock input for JTAG interface with internal pull-up.
9	TDO	output	Test Data Output for JTAG interface.
10	TMS	input	Test Mode Select input for JTAG interface with internal pull-up.
11	TRST#	input	Active low Test Reset input for JTAG interface with internal pull-up.
12	TDI	input	Test Data Input for JTAG interface with internal pull-up.
13	RD-	bidirectional	Differential receive input (PMD Input Pair); usable as transmit output in Auto-MDIX mode or 100BASE-FX receive pair with 3.3 V bias requirement.
14	RD+	bidirectional	Differential receive input (PMD Input Pair); usable as transmit output in Auto-MDIX mode or 100BASE-FX receive pair with 3.3 V bias requirement.
15	CD_VSS	power_in	Analog ground for Common Driver circuit.
16	TD-	bidirectional	Differential transmit output (PMD Output Pair) for 10BASE-T or 100BASE-TX; usable as receive input in Auto-MDIX mode or 100BASE-FX transmit pair with 3.3 V bias.
17	TD+	bidirectional	Differential transmit output (PMD Output Pair) for 10BASE-T or 100BASE-TX; usable as receive input in Auto-MDIX mode or 100BASE-FX transmit pair with 3.3 V bias.
18	ANAVSS	power_in	Analog ground supply.
19	ANA33VDD	power_out	Analog VDD supply; 3.3 Volts ±0.3 V or 3.3 Volts ±10%.
20	VREF	power_in	Bias resistor connection point; connect 4.87 kΩ 1% resistor from VREF to GND.
21	CLK_OUT_EN	input	Clock Output Enable strapping pin with internal pull-down; high enables clock output on CLK_OUT at power-up.
22	PCF_EN	input	PHY Control Frame Enable strapping pin with internal pull-down; high allows device to respond to PHY Control Frames.
23	RESERVED	unconnected	Reserved pin; should not be connected to external logic or net for most implementations.
24	CLK_OUT	output	Configurable clock output providing 50 MHz RMII reference in Master Mode, 25 MHz Receive Clock in 100 Mb mode, or 25/50 MHz pass-through of X1 reference clock.
25	RESERVED	unconnected	Reserved pin; should not be connected to external logic or net for most implementations.
26	LED_ACT	output	Activity/Collision/Duplex LED output with internal pull-up; Mode 1 indicates activity, Mode 2/3 indicates collision detection or full-duplex status.
27	LED_SPEED/FX_SD	output	Speed/Fiber Signal Detect LED output with internal pull-up; ON at 100 Mb/s and OFF at 10 Mb/s, or serves as fiber signal detect input in 100BASE-FX mode.
28	LED_LINK	output	Link/Activity LED output with internal pull-up; indicates link status and optional transmit/receive activity based on LED mode configuration.
29	RESET_N	input	Active low Reset input with internal pull-up; assert low for minimum 1 µs to initialize all registers and strap options to default states.
30	MDIO	bidirectional	Management Data I/O; bidirectional serial management instruction/data signal requiring 1.5 kΩ pullup resistor or internal pullup via CDCTRL1 register bit 3.
31	MDC	input	Management Data Clock input; synchronous clock to MDIO interface with maximum 25 MHz rate and no minimum clock rate.
32	IO_VDD	power_out	I/O VDD supply; 3.3 Volts ±0.3 V, 3.3 Volts ±10%, or 2.5 Volts ±5%.
33	X2	output	Crystal output; connects to external 25 MHz crystal resonator device or left unconnected if external CMOS oscillator is used.
34	X1	input	Crystal/Oscillator input; primary 25 MHz ±50 ppm reference (or 50 MHz for RMII Slave) from external crystal resonator or CMOS-level oscillator source.
35	IO_CORE_VSS	power_in	Digital ground for core I/O circuits.
36	RESERVED	unconnected	Reserved pin; should not be connected to external logic or net for most implementations.
37	RESERVED	unconnected	Reserved pin; should not be connected to external logic or net for most implementations.
38	RX_CLK	output	25 MHz MII Receive Clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode with integrated 50 ohm termination.
39	RX_DV	output	MII Receive Data Valid output with internal pull-down; asserted high when valid data present on RXD[3:0] with integrated 50 ohm termination.
40	CRS/CRS_DV	output	MII Carrier Sense or RMII Carrier Sense/Receive Data Valid output with internal pull-up; asserts high for receive medium non-idle with 50 ohm termination.
41	RX_ER	output	MII Receive Error output with internal pull-up; asserted high synchronously to RX_CLK indicating invalid symbol detection with integrated 50 ohm termination.
42	COL	output	Collision Detect output with internal pull-up; asserts high for collision detection in half-duplex modes or heartbeat in 10 Mb half-duplex with 50 ohm termination.
43	RXD_3	output	MII Receive Data output bit 3 with internal pull-down; driven synchronously to RX_CLK containing valid data when RX_DV asserted.
44	RXD_2	output	MII Receive Data output bit 2 with internal pull-down; driven synchronously to RX_CLK containing valid data when RX_DV asserted.
45	RXD_1	output	MII Receive Data output bit 1 with internal pull-down; driven synchronously to RX_CLK containing valid data when RX_DV asserted.
46	RXD_0	output	MII Receive Data output bit 0 with internal pull-down; driven synchronously to RX_CLK containing valid data when RX_DV asserted.
47	IO_VSS	power_in	Digital ground.
48	IO_VDD	power_out	I/O VDD supply; 3.3 Volts ±0.3 V, 3.3 Volts ±10%, or 2.5 Volts ±5%.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-48-EP(7x7)
Category	Interface
Pins	49

CAD (KiCad official)

Symbol: DP83620SQX
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: dp83620sqx-etched.step / dp83620sqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dp83620sqx.step / dp83620sqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (108 pp, sha256 2fb105d27fcfbe46, retrieved 2026-10-01, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF