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TPS53819ARGTR

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Texas Instruments DC-DC Converters, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps53819argtrfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TPS53819ARGTR

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TPS53819ARGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCL input PMBus clock input operating from 0 to 5.5 V.
2 SDA bidirectional PMBus data I/O (open-drain) operating from 0 to 5.5 V with low-level hysteresis of 240 mV.
3 ALERT output Open-drain alert output for PMBus interface (0.4 V low-level output at 5.5 V supply).
4 TRIP bidirectional OCL detection threshold pin sourcing 10-µA temperature-compensated current (4700 ppm/°C) with 0.2 to 3 V operating range.
5 VO input Output voltage monitoring input operating from 0 to 5.5 V.
6 FB input Output voltage feedback input connected to resistor divider between output and GND, 600 mV reference, -1 to 1 µA leakage current.
7 GND power_in Ground connection for the device.
8 VDD power_in Controller power supply input with 4.5 to 28 V operating range and programmable UVLO threshold from 4.1 to 10.2 V.
9 VREG power_out 5-V low-dropout output (4.5 to 5.5 V) supplying bias voltage to internal analog circuits and gate drivers with 152 mA overcurrent limit.
10 DRVL output Synchronous MOSFET gate driver output (referenced to GND) with 0.9 Ω source and 0.5 Ω sink resistance, 10 ns dead time to DRVH.
11 DRVH output High-side MOSFET gate driver output (referenced to SW node) with 1.6 Ω source and 0.6 Ω sink resistance, 20 ns dead time from DRVL.
12 SW power_out Switching node for buck converter inductor connection, operating from -3 to 30 V DC with up to 40 A output current capability.
13 VBST power_out Bootstrap supply for high-side gate driver (referenced to SW), operating from -0.1 to 5.5 V relative to SW with 1.5 µA maximum leakage current.
14 EN input Enable input with 0.5 V low threshold and 1.8 V high threshold, 0.22 V hysteresis, operating from 0 to 6.5 V.
15 PGOOD output Open-drain power-good status output active high when FB within ±8% of target, with programmable delay from 0.25 to 131 ms and 6.9 mA sink current.
16 ADDR input PMBus address select input via resistor divider between VREG and GND, supporting 16 different addresses (001A3A2A1A0x format), operating from 0 to 5.5 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VBST -0.3 38 V 4
Input voltage VBST -0.3 6 V With respect to SW terminal (note 3) 4
Input voltage EN -0.3 7.7 V 4
Input voltage VDD -0.3 30 V 4
Input voltage SW SW -3 32 V DC 4
Input voltage SW SW -5 32 V Pulse < 30% of the repetitive period 4
Output voltage DRVH DRVH -3 38 V DC 4
Output voltage DRVH DRVH -5 38 V Pulse < 30% of the repetitive period 4
Output voltage DRVH(3), DRVL DRVH, DRVL -0.3 6 V DRVH with respect to SW (note 3) 4
ALERT, VREG, TRIP ALERT, VREG, TRIP -0.3 6 V 4
PGOOD PGOOD -0.3 7.7 V 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -55 150 °C 4
Input voltage range VBST -0.1 35.5 V 4
Input voltage range VBST -0.1 5.5 V 4
Input voltage range EN -0.1 6.5 V 4
Input voltage range VDD 4.5 28 V 4
Input voltage range SW SW -3 30 V DC 4
Input voltage range SW SW -4.5 30 V Pulse < 30% of the repetitive period 4
Output voltage range DRVH DRVH -3 35.5 V DC 4
Output voltage range DRVH DRVH -4.5 35.5 V Pulse < 30% of the repetitive period 4
Output voltage range DRVH(1), DRVL DRVH, DRVL -0.1 5.5 V 4
Output voltage range ALERT, VREG ALERT, VREG -0.1 5.5 V 4
Output voltage range PGOOD PGOOD -0.1 6.5 V 4
Operating free-air temperature TA -40 85 °C 4
Feedback voltage tolerance VFBTOL 597 600 603 mV FB w/r/t GND, 0°C ≤ TJ ≤ 85°C 5
DAC voltage tolerance 1 VDACTOL1 -4.8 4.8 mV FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_ADJUSTMENT only 5
DAC voltage tolerance 2 VDACTOL2 -4.8 4.8 mV FB w/r/t GND, 0°C ≤ TA ≤ 85°C, all settings with VOUT_MARGIN only 5
DAC voltage tolerance 3 VDACTOL3 -4.8 4.8 mV FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 0Dh and VOUT_MARGIN = 70h for +5% 5
DAC voltage tolerance 4 VDACTOL4 -4.8 4.8 mV FB w/r/t GND, 0°C ≤ TA ≤ 85°C, with VOUT_ADJUSTMENT = 13h and VOUT_MARGIN = 07h for -5% 5
Loop comparator input offset voltage VIOS_LPCMP -2.5 2.5 mV VREF to VFB, TA = 25°C 5
FB pin input current IFB -1 1 μA VFB = 600 mV 5
Powergood threshold, PGOOD in from higher VPGTH 105 108 111 % PGOOD in from higher 6
Powergood threshold, PGOOD in from lower VPGTH 89 92 95 % PGOOD in from lower 6
Powergood threshold, PGOOD out to higher VPGTH 113 116 119 % PGOOD out to higher 6
Powergood threshold, PGOOD out to lower VPGTH 81 84 87 % PGOOD out to lower 6
PGOOD leakage current IPGLK -1 0 1 μA VPGOOD = 5.0 V 6
EN input leakage current ILEAK -1 0 1 μA 6
TRIP source current ITRIP 9 10 11 μA TA = 25°C, VTRIP = 0.4 V, RDS(on) sensing 6
TRIP voltage range VTRIP 0.2 3 V RDS(on) sensing 6
Positive current limit threshold VOCLP 360 375 390 mV VTRIP = 3.0 V, RDS(on) sensing 6
Positive current limit threshold VOCLP 190 200 210 mV VTRIP = 1.6 V, RDS(on) sensing 6
Positive current limit threshold VOCLP 20 25 30 mV VTRIP = 0.2 V, RDS(on) sensing 6
Negative current limit threshold VOCLN -390 -375 -360 mV VTRIP = 3.0 V, RDS(on) sensing 6
Negative current limit threshold VOCLN -212 -200 -188 mV VTRIP = 1.6 V, RDS(on) sensing 6
Negative current limit threshold VOCLN -30 -25 -20 mV VTRIP = 0.2 V, RDS(on) sensing 6
OVP threshold voltage VOVP 117 120 123 % OVP detect voltage 6
UVP threshold voltage VUVP 65 68 71 % UVP detect voltage 6
VREG LDO output voltage VREG 4.5 5 5.5 V VIN = 12 V, ILOAD = 10 mA 6
VDD UVLO voltage VDDUVLO 4.1 4.25 4.4 V VDDINUVLO<2:0> = 101 7
Thermal resistance junction-to-ambient RθJA 51.3 °C/W 5
Thermal resistance junction-to-case (top) RθJC(top) 85.4 °C/W 5
Thermal resistance junction-to-board RθJB 20.1 °C/W 5
Junction-to-top characterization parameter ψJT 1.3 °C/W 5
Junction-to-board characterization parameter ψJB 19.4 °C/W 5
Thermal resistance junction-to-case (bottom) RθJC(bot) 6 °C/W 5

CAD (KiCad official)

  • Symbol: TPS53819ARGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps53819argtr-etched.step / tps53819argtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53819argtr.step / tps53819argtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 2d2dc1030a25c20b, retrieved 2026-09-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF