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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

TPS53819ARGTR

Texas Instruments · DC-DC Converters · VQFN-16-EP(3x3)

TPS53819ARGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCL	input	PMBus clock input operating from 0 to 5.5 V.
2	SDA	bidirectional	PMBus data I/O (open-drain) operating from 0 to 5.5 V with low-level hysteresis of 240 mV.
3	ALERT	output	Open-drain alert output for PMBus interface (0.4 V low-level output at 5.5 V supply).
4	TRIP	bidirectional	OCL detection threshold pin sourcing 10-µA temperature-compensated current (4700 ppm/°C) with 0.2 to 3 V operating range.
5	VO	input	Output voltage monitoring input operating from 0 to 5.5 V.
6	FB	input	Output voltage feedback input connected to resistor divider between output and GND, 600 mV reference, -1 to 1 µA leakage current.
7	GND	power_in	Ground connection for the device.
8	VDD	power_in	Controller power supply input with 4.5 to 28 V operating range and programmable UVLO threshold from 4.1 to 10.2 V.
9	VREG	power_out	5-V low-dropout output (4.5 to 5.5 V) supplying bias voltage to internal analog circuits and gate drivers with 152 mA overcurrent limit.
10	DRVL	output	Synchronous MOSFET gate driver output (referenced to GND) with 0.9 Ω source and 0.5 Ω sink resistance, 10 ns dead time to DRVH.
11	DRVH	output	High-side MOSFET gate driver output (referenced to SW node) with 1.6 Ω source and 0.6 Ω sink resistance, 20 ns dead time from DRVL.
12	SW	power_out	Switching node for buck converter inductor connection, operating from -3 to 30 V DC with up to 40 A output current capability.
13	VBST	power_out	Bootstrap supply for high-side gate driver (referenced to SW), operating from -0.1 to 5.5 V relative to SW with 1.5 µA maximum leakage current.
14	EN	input	Enable input with 0.5 V low threshold and 1.8 V high threshold, 0.22 V hysteresis, operating from 0 to 6.5 V.
15	PGOOD	output	Open-drain power-good status output active high when FB within ±8% of target, with programmable delay from 0.25 to 131 ms and 6.9 mA sink current.
16	ADDR	input	PMBus address select input via resistor divider between VREG and GND, supporting 16 different addresses (001A3A2A1A0x format), operating from 0 to 5.5 V.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-16-EP(3x3)
Category	Power Management (PMIC)
Pins	17

CAD (KiCad official)

Symbol: TPS53819ARGTR
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: tps53819argtr-etched.step / tps53819argtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps53819argtr.step / tps53819argtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (53 pp, sha256 2d2dc1030a25c20b, retrieved 2026-09-23, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF