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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

ACT88320QI109-T

Qorvo · Power Management - Specialized · QFN-32(4x4)

ACT88320QI109-T from Qorvo, in a QFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	Dedicated VIN power input for BUCK3; connect the BUCK3 input capacitors (10uF to PGND) directly to pins 1 and 2.
2	VIN	power_in	Dedicated VIN power input for BUCK3; connect the BUCK3 input capacitors (10uF to PGND) directly to pins 1 and 2.
3	SW_B3	power_out	Switch node pin for the BUCK3 regulator, connected directly to the buck inductor.
4	OVSNS	input	Analog VIN+ input used to monitor input voltage and start the inrush control FET; connect to PGND if the inrush FET is not used (absolute maximum 22V).
5	OVSNS_M	input	Analog VIN- input used to monitor current in the external sense resistor RSNS (current limit threshold 85mV); connect to PGND if the inrush FET is not used.
6	OVGATE	output	Gate drive for the inrush control FET, typically 8V above VIN, which requires a 12V n-channel FET.
7	PGND	power_in	Power ground for Buck3; connect the BUCK3 input capacitors directly to pins 7 and 8 and to the exposed pad.
8	PGND	power_in	Power ground for Buck3; connect the BUCK3 input capacitors directly to pins 7 and 8 and to the exposed pad.
9	SDA	bidirectional	I2C data input and output, open drain and requires a pull-up resistor.
10	SCL	input	I2C clock input.
11	GPIO4 / DVS	input	GPIO configured as a dynamic voltage scaling (DVS) input in CMI 109; open-drain capable and 5.5V tolerant.
12	GPIO3 / nIRQ	output	GPIO configured as an interrupt (nIRQ) open-drain output, needing a pull-up resistor.
13	GPIO1 / nRESET	output	GPIO configured as an nRESET open-drain output, released 20ms after Buck3 is in regulation in CMI 109.
14	GPIO2 / EXT_EN	output	GPIO configured as an open-drain output to enable an external power supply, going high 2.5ms after Buck2 is in regulation in CMI 109.
15	VIO	power_in	Digital input reference/bias voltage that powers the GPIO pins; bypass with a 1uF capacitor between VIO and AGND.
16	FB_B1	input	Feedback for the BUCK1 regulator; connect directly (Kelvin) to the Buck1 output capacitor.
17	VIN	power_in	Dedicated VIN power input for BUCK1; connect the Buck1 input capacitors directly to pins 17 and 18.
18	VIN	power_in	Dedicated VIN power input for BUCK1; connect the Buck1 input capacitors directly to pins 17 and 18.
19	SW_B1	power_out	Switch pin for the BUCK1 regulator, connected directly to the buck inductor.
20	SW_B1	power_out	Switch pin for the BUCK1 regulator, connected directly to the buck inductor.
21	PGND	power_in	Power ground for BUCK1 and BUCK2; connect the BUCK1 and BUCK2 input capacitors directly to this pin.
22	SW_B2	power_out	Switch pin for the BUCK2 regulator, connected directly to the buck inductor.
23	VIN	power_in	Dedicated VIN power input for BUCK2; connect the BUCK2 input capacitors directly to pins 23 and 24.
24	VIN	power_in	Dedicated VIN power input for BUCK2; connect the BUCK2 input capacitors directly to pins 23 and 24.
25	FB_B2	input	Feedback for the BUCK2 regulator; connect Kelvin to the Buck2 output capacitor.
26	PWREN	input	Power enable digital input, referenced to AVIN and 5.5V tolerant, with a 10us bidirectional filter.
27	AVIN	power_in	Dedicated VIN power input for LDO1 and LDO2 and analog VIN input; bypass to AGND with a 1uF ceramic capacitor.
28	OUT_LDO2	power_out	Output of the LDO2 regulator (200mA); bypass to AGND with a 1uF capacitor.
29	OUT_LDO1	power_out	Output of the LDO1 regulator (200mA); bypass to AGND with a 1uF capacitor.
30	LSG1	output	Output1 load switch gate driver for an external n-channel FET with programmable 2.5uA to 10uA slew current and a 75 ohm pulldown when disabled.
31	AGND	power_in	Analog ground for the analog circuitry and LDOs; must be connected to the exposed pad.
32	FB_B3	input	Feedback for the BUCK3 regulator; connect Kelvin to the Buck3 output capacitor.
33	Exposed Pad	power_in	Exposed pad ground reference that must be soldered to the top layer ground plane, with all ground pins connected to it.

Key specifications

Parameter	Value
Manufacturer	Qorvo
Package	QFN-32(4x4)
Category	Power Management (PMIC)
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input Supply Voltage Range AVIN	AVIN	2.7		5.5	V	referenced to AGND	9
UVLO Threshold Falling		2.5	2.6	2.7	V		9
OV Threshold Rising		5.5	5.75	6	V		9
OV Hysteresis		100	200	300	mV		9
Thermal Shutdown Temperature		140	160	180	°C	Temperature rising	9
Oscillator Frequency		2.13	2.25	2.37	MHz		9
Operating Supply Current, all regulators disabled				10	µA	All Regulators Disabled	9
Operating Supply Current, all regulators enabled				250	µA	All Regulators Enabled but no load	9
Buck1 Output Voltage Accuracy PWM		-1		1	%	VOUT_B1 = default CMI voltage, continuous PWM mode	12
Buck1 Output Voltage Accuracy PFM		-2		2	%	VOUT_B1 = default CMI voltage, PFM mode	12
Buck1 Current Limit, Cycle-by-Cycle		4.14	4.6	5.06	A		12
Buck1 PMOS On-Resistance			40	50	mΩ	ISW = -1A, VIN = 5.0V	12
Buck1 NMOS On-Resistance			16	25	mΩ	ISW = 1A, VIN = 5.0V	12
Buck1 Power Good Threshold		90	92.5	95	%VNOM	VOUT_B1 Rising	12
Buck1 Soft-Start Period	Tset	480		600	µs	10% to 90% VNOM	12
Buck2-3 Output Voltage Accuracy		-1		1	%	VOUTx = default CMI voltage, IOUTx = 1A (continuous PWM mode)	14
Buck2-3 Current Limit, Cycle-by-Cycle		2.7	3	3.3	A		14
Buck2-3 Power Good Threshold		90	92.5	95	%VNOM	VOUTx Rising	14
LDO Output Voltage Accuracy		-1		1	%	AVIN - VLDOx_OUT > 0.4V	15
LDO Output Current		180	200		mA		15
Overcurrent Shutdown Threshold (inrush)		70	85	100	mV	Voltage across current sense resistor	11
Absolute Max: All Pins to AGND and PGND		-0.3		6	V	unless stated otherwise	7
Absolute Max: OVSNS, OVSNS_M to PGND		-0.3		22	V		7
Absolute Max: OVGATE to VIN		-0.3		13.2	V		7
Absolute Max: VIN to PGND		-0.3		6	V		7
Operating Junction Temperature		-40		150	°C		7
Storage Temperature		-55		150	°C		7
Junction to Ambient Thermal Resistance			26.5		°C/W	Measured on Active-Semi Evaluation Kit	7
Junction to Case Thermal Resistance			13.1		°C/W	Measured on Active-Semi Evaluation Kit	7

CAD (KiCad official)

Symbol: ACT88320QI109-T
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32(4x4) (KiCad packages3D, STEP)
3D model files: act88320qi109-t-etched.step / act88320qi109-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); act88320qi109-t.step / act88320qi109-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Qorvo datasheet (57 pp, sha256 2209f7c7460e5025, retrieved 2026-10-24, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF