Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

TPS54356PWPR

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

TPS54356PWPR from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply voltage requiring 4.5 V to 20 V with low-ESR 10 µF ceramic bypass capacitor placed close to device pins.
2 VIN power_in Input supply voltage requiring 4.5 V to 20 V with low-ESR 10 µF ceramic bypass capacitor placed close to device pins.
3 UVLO input Undervoltage lockout input with internal voltage divider that can be overridden by external resistive divider from VIN to ground.
4 PWRGD tri_state Open-drain power good output asserted low when output voltage falls below nominal or fault conditions detected with internal rising-edge filter.
5 RT input Frequency setting input programmed by grounding for 250 kHz, floating for 500 kHz, or connecting 69-215 kΩ resistor to ground for 250-700 kHz.
6 SYNC bidirectional Bidirectional synchronization I/O outputting falling-edge signal when RT floating/grounded or accepting external synchronization input when RT resistor used with required 10 kΩ ground resistor.
7 ENA input Enable control input stopping device switching when pulled below 0.5 V threshold with float enabling operation.
8 COMP output Error amplifier output internal node with 1.5 mA drive capability that must not be connected externally.
9 VSENSE input Feedback network input node compared to internal voltage reference for output voltage regulation.
10 AGND power_in Analog ground return for sensitive analog circuitry that must connect to PGND and PowerPAD.
11 PGND power_in Power ground return for LSG driver output currents that must connect to AGND and PowerPAD.
12 VBIAS power_out Internal bias voltage output providing 8.0 V at VIN ≥12 V or 4.4 V at VIN = 4.5 V requiring 1.0 µF ceramic bypass capacitor.
13 LSG output Low-side MOSFET gate driver output with 100 mA source/sink capability connecting to n-channel MOSFET gate or left open for diode-only configuration.
14 PH output Phase node switching output with voltage range from −1.5 V to +22 V connecting to external L-C output filter inductance.
15 PH output Phase node switching output with voltage range from −1.5 V to +22 V connecting to external L-C output filter inductance.
16 BOOT output Bootstrap supply connection for high-side gate driver with 0.1 µF ceramic capacitor connecting from BOOT to PH pins.
17 PowerPAD power_in Exposed thermal pad for junction-to-ambient heat dissipation that must solder to PGND and AGND connections.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Supply Chip
Pins 17

CAD (KiCad official)

  • Symbol: TPS54356PWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: tps54356pwpr-etched.step / tps54356pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps54356pwpr.step / tps54356pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 1e7f079dce00c4b2, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF