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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

L6470HTR

STMicroelectronics · Stepper Motor Driver · HTSSOP-28

L6470HTR from STMicroelectronics, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT1A	power_out	Full bridge A phase output 1 capable of sourcing or sinking up to 7 A peak current with programmable slew rate control.
2	VSA	power_in	Full bridge A power supply input pin requiring 8-45 V supply voltage and must be connected to VSB.
3	STBY\RST	input	Active-low standby and reset pin that resets logic and disables charge pump when driven low; must be connected to VDD if not used.
4	SW	input	External switch input pin with internal 60-110 kΩ pull-up resistor for user-defined interrupt control; must be connected to VDD if not used.
5	ADCIN	input	Integrated analog-to-digital converter input pin accepting 0-VREG voltage range with 5-bit resolution sampled at PWM frequency.
6	VREG	power_in	Internal 3 V voltage regulator output and external 3.3 V logic supply pin capable of sourcing 40 mA with 50 mV maximum dropout; requires 22-47 µF bypass capacitor.
7	OSCIN	input	Oscillator input pin for connecting external crystal/resonator (8-32 MHz) or direct clock source; leave floating if using internal oscillator.
8	OSCOUT	output	Oscillator output pin providing 2/4/8/16 MHz clock from internal oscillator or crystal/resonator driving capability with 4 mA maximum output current.
9	AGND	power_in	Analog ground reference pin internally connected to PGND and DGND; differential voltage between AGND and DGND must not exceed ±0.3 V.
10	CP	output	Charge pump oscillator output pin supplying signal for external charge pump circuit with 660-800 kHz oscillation frequency.
11	VBOOT	power_in	Bootstrap voltage supply pin (maximum 55 V) for high-side gate drivers requiring 1.1-1.4 mA average charging current.
12	VSB	power_in	Full bridge B power supply input pin requiring 8-45 V supply voltage and must be connected to VSA.
13	PGND	power_in	Power ground reference pin for motor output stage; differential voltage between PGND and DGND must not exceed ±0.3 V.
14	OUT1B	power_out	Full bridge B phase output 1 capable of sourcing or sinking up to 7 A peak current with programmable slew rate control.
15	OUT2B	power_out	Full bridge B phase output 2 capable of sourcing or sinking up to 7 A peak current with programmable slew rate control.
16	VSB	power_in	Full bridge B power supply input pin requiring 8-45 V supply voltage and must be connected to VSA; duplicate connection for current distribution.
17	VDD	power_in	Logic power supply voltage (3.3 V or 5 V) for output driver pull-up reference; requires 10 µF bypass capacitor for proper operation.
18	SDO	output	SPI serial data output pin with 0.3 V maximum low voltage and 2.4 V minimum high voltage at 3.3 V VDD; maximum drive current 4 mA.
19	CK	input	SPI serial clock input pin (TTL/CMOS compatible, 3.3-5 V logic levels) with maximum frequency 5 MHz and 0.8-2 V logic thresholds.
20	SDI	input	SPI serial data input pin (TTL/CMOS compatible, 3.3-5 V logic levels) sampled on CK rising edges with 25 ns setup and 20 ns hold time.
21	DGND	power_in	Digital ground reference pin for logic circuitry; differential voltage between DGND and AGND must not exceed ±0.3 V.
22	BUSY\SYNC	tri_state	Open-drain output pin functioning as busy flag (pulled low during command execution) or synchronization clock signal based on SYNC_EN bit.
23	CS	input	SPI chip select input pin (active low, TTL/CMOS compatible) with 335-565 kΩ internal pull-up resistance and 350 ns setup time.
24	FLAG	tri_state	Open-drain output pin (active low) for alarm condition signaling on overcurrent, thermal shutdown/warning, UVLO, stall detection, switch events, or command errors.
25	STCK	input	Step-clock input pin (TTL/CMOS compatible, 3.3-5 V logic levels) for external pulse counting mode with maximum input frequency 2 MHz.
26	VSA	power_in	Full bridge A power supply input pin requiring 8-45 V supply voltage and must be connected to VSB; duplicate connection for current distribution.
27	PGND	power_in	Power ground reference pin for motor output stage; differential voltage between PGND and DGND must not exceed ±0.3 V; duplicate connection for current distribution.
28	OUT2A	power_out	Full bridge A phase output 2 capable of sourcing or sinking up to 7 A peak current with programmable slew rate control.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-28
Category	Motor Driver ICs
Pins	29

CAD (KiCad official)

Symbol: L6470HTR
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28 (KiCad packages3D, STEP)
3D model files: l6470htr-etched.step / l6470htr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6470htr.step / l6470htr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (73 pp, sha256 4b94ab59eec71372, retrieved 2026-09-23, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF