component
C8051F912-D-GM
Public Made by Adomby adom
SKYWORKS/SILICON LABS Microcontroller Units (MCUs/MPUs/SOCs), QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownC8051F912-D-GM
SKYWORKS/SILICON LABS · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-24(4x4)
C8051F912-D-GM from SKYWORKS/SILICON LABS, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DC-/GND | power_in | DC-DC converter return current path, typically not connected to ground in single-cell battery mode and must be connected directly to ground in dual-cell battery mode. |
| 2 | GND | power_in | Required ground connection. |
| 3 | VDD/DC+ | power_in | Power supply voltage that must be 1.8 to 3.6 V and always be greater than VBAT; in single-cell mode this pin is the positive dc-dc converter output and needs a 1 uF ceramic capacitor between DC+ and DC- (it can supply external devices in single-cell mode). |
| 4 | DCEN | power_in | DC-DC enable pin: in single-cell battery mode it must be connected to VBAT through a 0.68 uH inductor, and in dual-cell battery mode it must be connected directly to ground. |
| 5 | VBAT | power_in | Battery supply voltage: must be 0.9 to 1.8 V in single-cell and 1.8 to 3.6 V in dual-cell mode on C8051F911/01, and 0.9 to 3.6 V in single-cell and 1.8 to 3.6 V in dual-cell mode on C8051F912/02. |
| 6 | RST/C2CK | bidirectional | Open-drain reset output from the internal POR or VDD monitor that an external source can drive low for at least 15 us to reset the device, with a 1 k to 5 k pullup to VDD recommended; the same pin is the C2 debug interface clock. |
| 7 | P2.7/C2D | bidirectional | Port 2.7 GPIO only (the Crossbar cannot route to it and it cannot be an analog input), also serving as the C2 debug data signal; available only on C8051F912/02. |
| 8 | XTAL4 | output | SmaRTClock oscillator crystal output. |
| 9 | XTAL3 | input | SmaRTClock oscillator crystal input. |
| 10 | P1.6 | bidirectional | Port 1.6 GPIO pin (digital I/O or analog input per Port I/O configuration). |
| 11 | P1.5 | bidirectional | Port 1.5 GPIO pin (digital I/O or analog input per Port I/O configuration). |
| 12 | P1.4 | bidirectional | Port 1.4 GPIO pin (digital I/O or analog input per Port I/O configuration). |
| 13 | P1.3 | bidirectional | Port 1.3 GPIO pin; may also be used as NSS for SPI1. |
| 14 | P1.2 | bidirectional | Port 1.2 GPIO pin; may also be used as MOSI for SPI1. |
| 15 | P1.1 | bidirectional | Port 1.1 GPIO pin; may also be used as MISO for SPI1. |
| 16 | P1.0 | bidirectional | Port 1.0 GPIO pin; may also be used as SCK for SPI1. |
| 17 | P0.7/IREF0 | bidirectional | Port 0.7 GPIO pin; alternatively the IREF0 current reference output. |
| 18 | P0.6/CNVSTR | bidirectional | Port 0.6 GPIO pin; alternatively the external convert start input for ADC0. |
| 19 | P0.5/RX | bidirectional | Port 0.5 GPIO pin; alternatively the UART RX input. |
| 20 | P0.4/TX | bidirectional | Port 0.4 GPIO pin; alternatively the UART TX output. |
| 21 | P0.3/XTAL2/WAKEOUT | bidirectional | Port 0.3 GPIO pin; alternatively the external oscillator excitation driver (XTAL2), an external clock input, or the WAKEOUT wake-up request signal (C8051F912/02 only). |
| 22 | P0.2/XTAL1/RTCOUT | bidirectional | Port 0.2 GPIO pin; alternatively the external oscillator return for a crystal or resonator (XTAL1), or the buffered SmaRTClock output RTCOUT (C8051F912/02 only). |
| 23 | P0.1/AGND | bidirectional | Port 0.1 GPIO pin; alternatively the optional analog ground reference AGND. |
| 24 | P0.0/VREF | bidirectional | Port 0.0 GPIO pin; alternatively the external VREF input or the internal VREF output, with external VREF decoupling capacitors recommended. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SKYWORKS/SILICON LABS |
| Package | QFN-24(4x4) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature under bias | -55 | 125 | °C | 36 | |||
| Storage Temperature | -65 | 150 | °C | 36 | |||
| Voltage on any Port I/O Pin or RST with respect to GND | -0.3 | 5.8 | V | VDD > 2.2 V | 36 | ||
| Voltage on any Port I/O Pin or RST with respect to GND | -0.3 | V | VDD < 2.2 V (max printed as VDD + 3.6 V) | 36 | |||
| Voltage on VBAT with respect to GND | VBAT | -0.3 | 4 | V | One-Cell Mode (F912/02) | 36 | |
| Voltage on VDD/DC+ with respect to GND | VDD/DC+ | -0.3 | 4 | V | 36 | ||
| Maximum total current through VBAT, DCEN, VDD/DC+ or GND | 500 | mA | 36 | ||||
| Maximum current through RST or any Port pin | 100 | mA | 36 | ||||
| Maximum total current through all Port pins | 200 | mA | 36 | ||||
| DC-DC Converter Output Power | 110 | mW | 36 | ||||
| Battery Supply Voltage (VBAT) | VBAT | 0.9 | 1.2 | 3.6 | V | One-Cell Mode (F912/02) | 37 |
| Battery Supply Voltage (VBAT) | VBAT | 1.8 | 2.4 | 3.6 | V | Two-Cell Mode | 37 |
| Supply Voltage (VDD/DC+) | VDD/DC+ | 1.8 | 1.9 | 3.6 | V | One-Cell Mode | 37 |
| Supply Voltage (VDD/DC+) | VDD/DC+ | 1.8 | 2.4 | 3.6 | V | Two-Cell Mode | 37 |
| Minimum RAM Data Retention Voltage (VBAT in Sleep Mode) | 0.3 | 0.5 | V | VBAT (in Sleep Mode) | 37 | ||
| SYSCLK (System Clock) | SYSCLK | 0 | 25 | MHz | 37 | ||
| TSYSH (SYSCLK High Time) | TSYSH | 18 | ns | 37 | |||
| TSYSL (SYSCLK Low Time) | TSYSL | 18 | ns | 37 | |||
| Specified Operating Temperature Range | -40 | 85 | °C | 37 | |||
| Digital Supply Current, CPU Active (Normal Mode) | IDD | 4 | 5 | mA | VDD = 1.8-3.6 V, F = 24.5 MHz (includes precision oscillator current) | 38 | |
| Digital Supply Current, CPU Inactive (Idle Mode) | IDD | 2.1 | 3 | mA | VDD = 1.8-3.6 V, F = 24.5 MHz (includes precision oscillator current) | 38 | |
| RST Output Low Voltage | 0.6 | V | IOL = 1.4 mA | 52 | |||
| RST Input Low Voltage | 0.6 | V | VDD = 2.0 to 3.6 V | 52 | |||
| RST Input Pullup Current | 20 | 35 | µA | RST = 0.0 V, VDD = 3.6 V | 52 | ||
| VDD/DC+ Monitor Threshold (VRST) | VRST | 1.8 | 1.85 | 1.9 | V | Early Warning | 52 |
| VDD/DC+ Monitor Threshold (VRST) | VRST | 1.7 | 1.75 | 1.8 | V | Reset Trigger (all power modes except Sleep) | 52 |
| VBAT Ramp Time for Power On | 3 | ms | VBAT Ramp from 0-0.9 V | 52 | |||
| VBAT Monitor Threshold (VPOR) | VPOR | 0.9 | 1 | 1.1 | V | Early Warning | 52 |
| VBAT Monitor Threshold (VPOR) | VPOR | 0.7 | 0.8 | 0.9 | V | Brownout Condition (VBAT Falling) | 52 |
| Missing Clock Detector Timeout | 100 | 525 | 1000 | µs | Time from last system clock rising edge to reset initiation | 52 | |
| Minimum System Clock w/ Missing Clock Detector Enabled | 2 | 10 | kHz | System clock frequency which triggers a missing clock detector timeout | 52 | ||
| Minimum RST Low Time to Generate a System Reset | 15 | µs | 52 | ||||
| Idle Mode Wake-up Time | 2 | 3 | SYSCLKs | 53 | |||
| Flash Size | 16384 | bytes | C8051F912/1 | 53 | |||
| Scratchpad Size | 512 | 512 | bytes | 53 | |||
| Endurance | 1 | 90 | k Erase/Write Cycles | 53 | |||
| Erase Cycle Time | 28 | 32 | 36 | ms | 53 | ||
| Write Cycle Time | 57 | 64 | 71 | µs | 53 | ||
| Oscillator Frequency (internal precision oscillator) | 24 | 24.5 | 25 | MHz | -40 to +85 °C, VDD = 1.8-3.6 V | 53 | |
| Oscillator Frequency (internal low-power oscillator) | 18 | 20 | 22 | MHz | -40 to +85 °C, VDD = 1.8-3.6 V | 53 | |
| Oscillator Frequency (LFO) | 13.1 | 16.4 | 19.7 | kHz | 54 | ||
| Integral Nonlinearity | -1.5 | 1 | 1.5 | LSB | 12-bit mode | 54 | |
| Integral Nonlinearity | -1 | 0.5 | 1 | LSB | 10-bit mode | 54 | |
| Differential Nonlinearity (Guaranteed Monotonic) | -1 | 0.8 | 1 | LSB | 12-bit mode | 54 | |
| Differential Nonlinearity (Guaranteed Monotonic) | -1 | 0.5 | 1 | LSB | 10-bit mode | 54 | |
| Full Scale Error | -4 | 1 | 4 | LSB | 12-bit mode | 54 | |
| Full Scale Error | -2.5 | 1 | 2.5 | LSB | 10-bit mode | 54 | |
| Signal-to-Noise Plus Distortion | 62 | 65 | dB | 10 kHz sine-wave single-ended input, 1 dB below Full Scale, maximum sampling rate; 12-bit mode | 54 | ||
| SAR Conversion Clock (Normal Mode) | 8.33 | MHz | Normal Mode | 54 | |||
| SAR Conversion Clock (Low Power Mode) | 4.4 | MHz | Low Power Mode | 54 | |||
| Throughput Rate | 300 | ksps | 10-bit mode | 54 | |||
| ADC Input Voltage Range, Single Ended (AIN+, GND) | 0 | V | 55 | ||||
| Input Low Voltage | 0.6 | V | VDD = 2.0 to 3.6 V | 47 | |||
| Output Low Voltage | 0.6 | V | High Drive Strength, PnDRV.n = 1, IOL = 8.5 mA | 47 | |||
| Input Leakage Current | -1 | 1 | µA | Weak Pullup Off | 47 | ||
| Input Voltage Range (DC-DC Converter, C8051F912/02) | 0.9 | 3.6 | V | C8051F912/02 | 60 | ||
| Output Voltage Range | 1.73 | 1.8 | 1.87 | V | Target Output = 1.8 V | 60 | |
| Clocking Frequency (DC-DC Converter) | 1.6 | 2.4 | 3.2 | MHz | 60 | ||
| Input Offset Voltage | -7 | 7 | mV | 58 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body | 34 |
CAD (KiCad official)
- Symbol:
C8051F912-D-GM - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
c8051f912-d-gm-etched.step/c8051f912-d-gm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);c8051f912-d-gm.step/c8051f912-d-gm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SKYWORKS/SILICON LABS datasheet (318 pp, sha256
d9f48e8306647ff2, retrieved 2026-10-31, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).