TMCS1123B1AQDVGR - Isolated Hall-Effect Current Sensor
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Texas Instruments TMCS1123B1AQDVGR: isolated Hall-effect current sensor, 25 mV/A with a 1.65 V zero-current output (linear +-62 A at 3.3 V), 80 A RMS continuous, 250 kHz, overcurrent detection, reinforced isolation, SOIC-10 wide body (DVG). KiCad, Fusion and Altium libraries, 3D model and datasheet.
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README
markdownTMCS1123B1AQDVGR
Texas Instruments · Isolated Hall-effect current sensor, 25 mV/A, 1.65 V zero-current output · SOIC-10 wide body (DVG)
TMCS1123B1AQDVGR is the B1A option of TI's TMCS1123: a galvanically isolated Hall-effect current sensor. The measured current flows through a 0.7 mOhm lead frame conductor between IN+ and IN-, on one side of a reinforced isolation barrier; the signal side runs from a single 3.0 V to 5.5 V supply and gives an analog output proportional to the current, a precision zero-current reference, a fast overcurrent comparator and a diagnostics output (SBOSA24D p.1, p.4). The B1A option has 25 mV/A sensitivity centred on 1.65 V, so on a 3.3 V supply it measures ±62 A linearly in both directions (p.3).
Key specifications
Values for TMCS1123BxA at VS = 3.3 V, TA = 25 C unless noted (TI characterizes the BxA parts at 3.3 V).
| Parameter | Value | Source |
|---|---|---|
| Sensitivity (B1A) | 25 mV/A; error ±0.1 % typ, ±0.4 % max | p.8 |
| Sensitivity drift | ±20 ppm/C typ, ±50 ppm/C max (thermal); ±0.2 % typ, ±0.5 % max (lifetime) | p.8 |
| Nonlinearity | ±0.1 % | p.8 |
| Zero-current output, VREF | 1.65 V; VREF error ±0.02 % typ, ±0.15 % max | p.8, p.9 |
| Offset error (x1A) | ±0.2 mV typ, ±1 mV max; drift ±2 uV/C typ, ±10 uV/C max | p.8 |
| Linear range (B1A) | ±62 A at VS = 3.3 V; -62 A to 130 A at VS = 5 V (output swing limit, not thermal) | p.3 |
| Conductor resistance | 0.7 mOhm (IN+ to IN-) | p.8 |
| Continuous current | 80 A RMS at 25 C, 44 A RMS at 125 C, on TI's TMCS1123xEVM (4 oz copper) | p.8, p.19, p.36 |
| Bandwidth, response | 250 kHz (-3 dB); 1 us response time; 110 ns propagation delay; 3 V/us slew | p.9 |
| Overcurrent detection | threshold VOC = S x IOC / 2.5 (0.3 V to VS); 100 ns typ, 250 ns max response; hysteresis 4.5 A (x1A); OC open-drain, active low | p.9, p.25 |
| ALERT diagnostics | open-drain, active low, 8 kHz PWM: 80 % duty thermal alert, 50 % sensor alert, 20 % both | p.9, p.28 |
| Supply | VS 3.0 V to 5.5 V; IQ 11 mA typ, 14 mA max (25 C); 14.5 mA max over temperature | p.5, p.9 |
| Power-on time | 34 ms from VS > 3 V to valid output | p.10 |
| Isolation | 5000 V RMS withstand (UL 1577, 60 s); reinforced working voltage 950 V RMS / 1343 V DC; VIORM 1697 V peak; VIOTM 7071 V peak; surge 10 kV peak | p.6 |
| Creepage, clearance, CTI | at least 8 mm external creepage and clearance; CTI at least 600 V, material group I | p.6 |
| CMTI | 150 kV/us | p.8 |
| Certifications | UL 1577 (file E181974); IEC/CB 62368-1 | p.6 |
| ESD | HBM ±4000 V, CDM ±1000 V | p.5 |
| Temperature | -40 C to +125 C operating; TJ max 165 C | p.5 |
| Thermal | RthJA 27.9 C/W, RthJB 10.1 C/W (on the EVM) | p.5 |
| Package | DVG (SOIC-10 wide body), 7.5 x 10.3 mm body, 10.3 x 10.3 mm with leads, 2.65 mm max height | p.1, p.45 |
| Moisture sensitivity, marking | MSL 2, 260 C peak; top marking 1123B1A |
p.40 |
Pinout (top view)
Pins 1 and 2 are the two wide current leads on one side of the package; pins 3 to 10 are on the other side, with 10 at the pin-1 end. The isolation barrier runs between the two rows.
| Pin | Name | Side of barrier | Type | Function |
|---|---|---|---|---|
| 1 | IN+ | primary (high voltage) | passive | Input current positive pin: one end of the 0.7 mOhm internal conductor (SBOSA24D p.4, Table 5-1; RIN p.8). Current flowing from IN+ to IN- gives a positive output change. This pin is on the primary (high-voltage) side of the isolation barrier. |
| 2 | IN- | primary (high voltage) | passive | Input current negative pin: the other end of the internal conductor (p.4, Table 5-1). Primary (high-voltage) side of the isolation barrier. |
| 3 | GND | isolated low voltage | power in | Ground of the isolated low-voltage side (p.4, Table 5-1). |
| 4 | ALERT | isolated low voltage | open collector | Sensor diagnostics output: open-drain, active low, 8 kHz PWM whose duty cycle reports thermal and sensor alerts (p.4; p.9; p.28). Connect to GND if not used. |
| 5 | VREF | isolated low voltage | output | Zero-current output voltage reference (1.65 V on BxA parts), for ratiometric or differential measurement of VOUT. Leave floating if not used (p.4; p.9). |
| 6 | VOUT | isolated low voltage | output | Output voltage: VOUT = VREF + S x IIN, linear from 100 mV to VS - 100 mV (p.4; p.24 Eq. 18 to 21). B1A: S = 25 mV/A, zero-current output 1.65 V. |
| 7 | OC | isolated low voltage | open collector | Overcurrent output, open-drain, active low. Needs a pull-up. Connect to GND if not used (p.4, Table 5-1). |
| 8 | VS | isolated low voltage | power in | Power supply, 3.0 V to 5.5 V (p.4; p.5 recommended operating conditions). Decouple to GND with 0.1 uF placed close to the pin (p.35). |
| 9 | VOC | isolated low voltage | input | Overcurrent threshold input: VOC = S x IOC / 2.5, 0.3 V to VS, 120 kOhm input impedance. Connect to VS if not used (p.4; p.9; p.25). |
| 10 | NC | isolated low voltage | no connect | Reserved. The datasheet allows it to be connected to GND or left floating (p.4, Table 5-1). Typed no-connect; tying it to GND is permitted by TI but will need an ERC waiver. |
Source: SBOSA24D p.4 (Figure 5-1, Table 5-1).
Variants
Every TMCS1123 option uses the same DVG package and pinout, so the footprint, 3D model and symbol on this page fit all of them; only the sensitivity, the zero-current output and therefore the linear range differ. Orderable part numbers add QDVGR (2000-piece tape and reel), for example TMCS1123B1AQDVGR (p.40). Linear range in amperes, from SBOSA24D Table 4-1 (p.3):
| Product | Sensitivity (mV/A) | Zero-current output (V) | Linear range, VS = 5 V (A) | Linear range, VS = 3.3 V (A) |
|---|---|---|---|---|
| TMCS1123A1A | 25 | 2.5 | ±96 (2) | -96 to 28 (2) |
| TMCS1123A2A | 50 | 2.5 | ±48 (2) | -48 to 14 (2) |
| TMCS1123A3A | 75 | 2.5 | ±32 | -32 to 9.3 |
| TMCS1123A4A | 100 | 2.5 | ±24 | -24 to 7 |
| TMCS1123A5A | 150 | 2.5 | ±16 | -16 to 4.7 |
| TMCS1123B1A (this page) | 25 | 1.65 | -62 to 130 (2) | ±62 (2) |
| TMCS1123B2A | 50 | 1.65 | -31 to 65 (2) | ±31 |
| TMCS1123B3A | 75 | 1.65 | -20.7 to 43.3 (2) | ±20.7 |
| TMCS1123B4A | 100 | 1.65 | -15.5 to 32.5 | ±15.5 |
| TMCS1123B5A | 150 | 1.65 | -10.3 to 21.7 | ±10.3 |
| TMCS1123C1A | 25 | 0.33 | -9.2 to 183 (2) | -9.2 to 115 (2) |
| TMCS1123C2A | 50 | 0.33 | -4.6 to 91.4 (2) | -4.6 to 57.4 (2) |
| TMCS1123C3A | 75 | 0.33 | -3.1 to 60.9 (2) | -3.1 to 38.3 (2) |
| TMCS1123C4A | 100 | 0.33 | -2.3 to 45.7 (2) | -2.3 to 28.7 |
| TMCS1123C5A | 150 | 0.33 | -1.5 to 30.5 | -1.5 to 19.1 |
| TMCS1123D71 (1) | 38.5 | 1.5 | -36.3 to 88.3 (2) | -36.3 to 44.1 (2) |
(1) D71: overcurrent output asserted only after a sustained event longer than the 1.25 us MASK time (p.3, p.9). (2) The current must also stay inside the continuous and transient safe operating areas (p.3, p.19 to p.21): the linear range can exceed what the part may carry continuously.
How to pick: the A options (2.5 V reference) suit bidirectional sensing on 5 V; the B options (1.65 V) suit bidirectional sensing on 3.3 V; the C options (0.33 V) are for unidirectional current. The range follows from VOUT between 100 mV and VS - 100 mV: IIN,max = (VS - 0.1 V - VREF) / S and IIN,min = (0.1 V - VREF) / S (p.24, Eq. 18 to 21). TI also sells automotive TMCS1123-Q1 parts (for example TMCS1123B1AQDVGRQ1) under their own datasheet; check that datasheet before substituting.
Design notes
- Creepage on the board. The part is rated for at least 8 mm creepage and clearance (p.6), but the PCB pads can reduce it. TI's land pattern has an IPC-7351 nominal option (7.3 mm between the pad rows) and an HV / isolation option (8.1 mm, p.46). This page uses the HV option and adds a copper keepout between the rows. Grooves or slots in the board can add creepage where a standard requires more (p.6 note 1).
- Current path and heat. The continuous rating is set by junction temperature on TI's EVM with 4 oz copper. Use large, heavy copper planes for IN+ and IN-, thermal via farms around the input and air flow to keep it (p.19, p.36).
- Supply and reference. Decouple VS with 0.1 uF close to the pin (p.35). VREF can drive up to 20 nF; VOUT up to 4.7 nF (p.8, p.9).
- Overcurrent threshold. Set VOC from a divider on VS or VREF with R2 under 10 kOhm (120 kOhm input impedance); add at least 500 Ohm between VREF and a 10 uF VOC capacitor (p.36, Figures 9-5 and 9-6). Tie VOC to VS when unused.
- Unused outputs. OC and ALERT to GND, VREF floating, VOC to VS, NC to GND or floating (p.4). The symbol types NC as no-connect, so a schematic that ties it to GND needs an ERC waiver.
CAD
| File | What it is |
|---|---|
| tmcs1123b1aqdvgr.kicad_sym | KiCad symbol TMCS1123B1AQDVGR (adom-symbol 1.2.6, every pin then moved onto the 2.54 mm grid): Primary side (IN+, IN-) on the left; the isolated low-voltage pins on the right in Supply, Analog output, Overcurrent and Reserved groups; chip outline drawn in the body. Properties: MPN, Manufacturer, Datasheet, Mouser, DigiKey, Adom Wiki. |
| tmcs1123b1aqdvgr.kicad_mod | KiCad footprint to TI's HV / isolation land pattern, with the isolation keepout rule area. Its 3D path is ${KIPRJMOD}/tmcs1123b1aqdvgr-etched.step; put the STEP beside your project or repoint the path. |
| tmcs1123b1aqdvgr.lbr | Fusion / EAGLE library (adom-lbr 2.47.6, lint PASS) with MPN, MANUFACTURER, DATASHEET, ADOM_WIKI, MOUSER_PN, DIGIKEY_PN attributes; the keepout is on tRestrict, bRestrict and vRestrict. |
| altium/TMCS1123B1AQDVGR.SchLib, altium/TMCS1123B1AQDVGR.PcbLib | Native Altium libraries (adom-lbr assemble-altium) with the etched STEP embedded in the footprint. Altium has no no-connect pin type, so NC is Passive there. The PcbLib has no keepout region (see Open items). |
| altium/TMCS1123B1AQDVGR.adom-lbr.json | The adom-lbr hub (symbol, footprint, pin to pad map) the Altium files are made from. |
| tmcs1123b1aqdvgr-etched.step | The library 3D model (see below). |
Footprint
The pads follow TI's HV / isolation option of the DVG0010A example board layout (SBOSA24D p.46, drawing 4226847/C): pads 1 and 2 are 1.65 x 4.41 mm at x = -4.875, y = ±2.54; pads 3 to 10 are 1.65 x 0.60 mm at x = +4.875, 1.27 mm pitch; R0.05 corners. That puts 8.1 mm of board between the primary pads and the low-voltage pads. A rule area on all copper layers (x -4.05 to +4.05 mm, y -5.5 to +5.5 mm) keeps tracks, vias and pours out of that strip. Every pad was compared with the drawing (provenance/footprint-check.json): all ten match.
Pin 1: pad 1 is the upper-left current pad in KiCad's footprint frame, with a silkscreen bar at the upper-left corner and a chamfer on the F.Fab outline. The 3D model's pin 1 lead lands on pad 1 with zero offset and rotation, and the pads run as in TI's top view (p.4): 1 and 2 down the left, 3 to 10 up the right.
Pads 1 and 2 are current terminals, not exposed thermal pads, so they have no vias in the pad; TI asks for via farms in the copper around the input instead (p.36). KiCad has no library footprint for this package; its SOIC-10 3.9 x 4.9 mm, 1 mm pitch footprint is a different part.
3D models
| File | What it is |
|---|---|
| tmcs1123b1aqdvgr-etched.step | Library model for board CAD: the package with the MPN etched on top in an Adom.LaserEtch group. |
| tmcs1123b1aqdvgr.step | The same package, unmarked. |
| tmcs1123b1aqdvgr-hero.glb | The page's 3D view: the etched model plus reference artwork (teal dashed pad outlines, silkscreen and pin-1 dot, signal names, and the isolation keepout as its own layer). Presentation only. |
| tmcs1123b1aqdvgr-etched.glb | Clean web and board-viewer copy of the etched model, matte-tin leads, no footprint artwork. |
| tmcs1123b1aqdvgr.glb | Web copy of the unmarked model. |
| lod/ | Four board detail levels (below). |
Frame for every file: Z up, seated on z = 0, centred on the footprint origin, pin 1 at (-x, +y), which is footprint pad 1.
How the model was made. TI's STEP for this package is on Ultra Librarian behind a reCAPTCHA and a terms form, so it was not downloaded. KiCad has no DVG0010A model. The model was therefore built from TI's package drawing (SBOSA24D p.45, DVG0010A, 4226847/C) with CadQuery (provenance/tools/build_dvg10.py): drafted epoxy body, two wide current leads and eight signal leads as radiused gull wings, pin-1 dimple inside TI's pin-1 ID area. It is AI-generated from the datasheet. Where TI gives a range the model takes the middle; dimensions TI does not give (parting line height, draft, bend radius) are chosen and listed in provenance/3d-model.json.
| Dimension (mm) | TI min / nom / max | Model |
|---|---|---|
| E overall lead span | 9.97 / - / 10.63 (TYP) | 10.30 |
| E1 molded width | 7.4 / - / 7.6 | 7.50 |
| D molded length | 10.1 / - / 10.5 | 10.30 |
| A overall height | max 2.65 | 2.55 |
| A1 standoff | 0.1 / - / 0.3 | 0.20 |
| c lead thickness | 0.23 / - / 0.32 (TYP) | 0.275 |
| b signal lead width | 0.31 / - / 0.51 | 0.41 |
| e signal pitch | 1.27 | 1.27 |
| Current lead width (pins 1, 2) | 4.12 / - / 4.32 | 4.22 |
| Current lead centre offset | 2.44 / - / 2.64 | 2.54 |
| Gap between current leads | (0.86) | 0.86 |
| L foot at the 0.25 mm gauge plane | 0.40 / - / 1.27 | 0.854 |
| Lead length, body to tip | (1.4) | 1.40 |
Measured on the STEP by plane sections (provenance/dims-model.json, provenance/dims-model-signal.json). The proof: the model's top, front and end views blended over TI's drawing at the drawing's own scale (calibrated on the printed E and D spans).
The marking is virtual. The etch reads TMCS1123 / B1AQDVGR, the orderable part number, so the part is identifiable in a 3D board view. TI's real marking is 1123B1A (p.40). The etch was made with adom-chip-laser (service-occt flat mark, 5 um above the top face), placed by the adom-aiflow-etch planner from the footprint; its gate passes.
Detail levels for board and digital-twin viewers
| Level | File | Marking |
|---|---|---|
| high | tmcs1123b1aqdvgr-high.glb | yes |
| medium | tmcs1123b1aqdvgr-medium.glb | yes |
| low | tmcs1123b1aqdvgr-low.glb | no |
| super-low | tmcs1123b1aqdvgr-super-low.glb | no |
All four share the library model's frame and carry no footprint, silkscreen or label artwork. High is the etched GLB; medium and low come from the same generator with each bend drawn as three straight segments (medium keeps the etch); super-low has an undrafted body and one-segment bends. Every level keeps all ten leads and the pin-1 dimple. Status: candidate; the previews were inspected, a streaming LOD viewer has not qualified them.
Symbol chip outline
The symbol body carries the chip outline drawn from the etched model by adom-aiflow-etch outline (gate PASS): artwork/TMCS1123B1AQDVGR-3d-outline-dark-named.svg.
Sourcing
Checked 2026-10-21 with adom-parts-search.
| Distributor | Part number | Stock | Price |
|---|---|---|---|
| Mouser | 595-TMCS1123B1AQDVGR | 0 (lead time 140 days) | 4.92 USD (1), 3.65 USD (100) |
| DigiKey | 296-TMCS1123B1AQDVGRTR-ND | 0 | 4.55 USD (1) |
| LCSC / JLCPCB | not listed | - | no JLCPCB/LCSC hit for this part number |
Mouser listed 4,000 of the automotive TMCS1123B1AQDVGRQ1 (595-CS1123B1AQDVGRQ1) on the same date; that is a different orderable part with its own datasheet. TI also sells directly at ti.com.
Packaging: 2000 per 330 mm reel, 16 mm tape, 12 mm pitch, pocket 10.75 x 10.7 x 2.7 mm, pin 1 in quadrant Q1 (p.43). MSL 2 (p.40).
Manufacturer and resources
| Resource | Link |
|---|---|
| Product page | ti.com/product/TMCS1123 |
| Datasheet | SBOSA24D (July 2023, revised May 2026), PDF on this page, ti.com |
| Package drawings | DVG0010A outline, example board layout and stencil, 4226847/C (datasheet p.45 to p.47) |
| Evaluation module | TMCS1123xEVM and its user's guide (linked from the product page) |
| CAD from TI | Ultra Librarian (TI embedded): symbol, footprint and STEP after a sign-off form |
| Related documentation | TI Isolation Glossary application note (cited on p.37) |
Related
- adom/tmcs1123a2aqdvgr: the A2A option (50 mV/A, 2.5 V reference). Its CAD files (2026-10-21) are KiCad's narrow SOIC-10 3.9 x 4.9 mm, 1 mm pitch footprint and model, which do not match TI's DVG package; the footprint and model on this page fit every TMCS1123 option.
Open items
- TI's own STEP was not compared (Ultra Librarian needs a browser sign-off).
- The Altium PcbLib has no keepout region: adom-lbr 2.47.6 does not carry the KiCad rule area. Draw a keepout region over x -4.05 to +4.05 mm in Altium or set it with a board rule.
- The libraries are checked by lint and read-back; they have not been opened in KiCad, Fusion or Altium.
Provenance
- Datasheet: TI SBOSA24D (July 2023, revised May 2026), 48 pages, sha256
66bab03ec907cb65, downloaded from ti.com on 2026-10-21 (docs/tmcs1123b1aqdvgr-datasheet.pdf). Every pin and spec above cites its page. - Footprint: provenance/footprint-check.json, pad by pad against p.46; made with adom-footprint 1.0.26 from provenance/tools/footprint-create.json, then fp_finish.py set the R0.05 corners, the keepout, the F.Fab pin-1 chamfer and the model path.
- 3D model: provenance/3d-model.json: source attempts, build parameters, measurements, overlay proof, etch gate, hashes. Tools in provenance/tools/; the lead construction and the GLB tools come from adom/mcp2562fd-e-sn.
- Hero: built with adom/component-hero's
hero_glb.py(adom-hero 1.4; alignment OK) and hero_post_keepout.py for the keepout layer; sidecar tmcs1123b1aqdvgr-hero.overlay.json. - Symbol: created from provenance/tools/symbol-create.json by adom-symbol 1.2.6, then every pin moved onto the 2.54 mm grid by snap_symbol.py (the tool placed the first pin of each column at y = -2.00 mm).
- Fusion keepout: added by lbr_keepout.py, because adom-lbr does not carry the rule area.
- Licence: Adom-authored files are CC-BY-4.0, see LICENSE. The datasheet and its page images are TI's and keep TI's terms.
Cited datasheet pages:
