component
SI2328DS-T1-GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSI2328DS-T1-GE3
Vishay Intertech · MOSFETs · SOT-23
SI2328DS-T1-GE3 from Vishay Intertech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate of the N-channel MOSFET; gate-source voltage is limited to ±20 V (absolute maximum), and the datasheet notes 100 % Rg tested. |
| 2 | S | passive | Source of the MOSFET; continuous source (diode conduction) current is rated at 0.6 A, and AN807 identifies pin 2 as the source. |
| 3 | D | passive | Drain of the MOSFET; drain-source voltage is rated at 100 V, and per AN807 the drain pin also provides the thermal connection from the package to the PC board. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Vishay Intertech |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VDS | 100 | V | VGS = 0 V, ID = 1 mA | 2 | ||
| Gate-Threshold Voltage | VGS(th) | 2 | 4 | V | VDS = VGS, ID = 250 µA | 2 | |
| Gate-Body Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | 1 | µA | VDS = 100 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 75 | µA | VDS = 100 V, VGS = 0 V, TJ = 70 °C | 2 | ||
| On-State Drain Current | ID(on) | 6 | A | VDS 15 V, VGS = 10 V | 2 | ||
| Drain-Source On-Resistance | RDS(on) | 0.195 | 0.25 | Ω | VGS = 10 V, ID = 1.5 A | 2 | |
| Gate Resistance | Rg | 0.5 | 1.3 | 2.4 | Ω | 2 | |
| Total Gate Charge | Qg | 3.3 | 5 | nC | VDS = 50 V, VGS = 10 V, ID = 1.5 A | 2 | |
| Turn-On Delay Time | td(on) | 7 | 11 | ns | VDD = 50 V, RL = 33 Ω, ID 0.2 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Rise Time | tr | 11 | 17 | ns | VDD = 50 V, RL = 33 Ω, ID 0.2 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 9 | 15 | ns | VDD = 50 V, RL = 33 Ω, ID 0.2 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Fall Time | tf | 10 | 15 | ns | VDD = 50 V, RL = 33 Ω, ID 0.2 A, VGEN = 10 V, Rg = 6 Ω | 2 | |
| Source-Drain Reverse Recovery Time | trr | 50 | 100 | ns | IF = 1.5 A, dI/dt = 100 A/µs | 2 | |
| Diode Forward Voltage | VSD | 0.8 | 1.2 | V | IS = 1 A, VGS = 0 V | 2 | |
| Drain-Source Voltage | VDS | 100 | V | 1 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current | ID | 1.5 | A | TJ = 150 °C, TA = 25 °C, 5 s | 1 | ||
| Continuous Drain Current | ID | 1.15 | A | TJ = 150 °C, TA = 25 °C, steady state | 1 | ||
| Continuous Drain Current | ID | 1.2 | A | TJ = 150 °C, TA = 70 °C, 5 s | 1 | ||
| Continuous Drain Current | ID | 0.92 | A | TJ = 150 °C, TA = 70 °C, steady state | 1 | ||
| Pulsed Drain Current | IDM | 6 | A | Pulse width limited by maximum junction temperature | 1 | ||
| Avalanche Current | IAS | 6 | A | L = 0.1 mH | 1 | ||
| Single Avalanche Energy | EAS | 1.8 | mJ | 1 | |||
| Continuous Source Current (Diode Conduction) | IS | 0.6 | A | 1 | |||
| Power Dissipation | PD | 1.25 | W | TA = 25 °C, 5 s | 1 | ||
| Power Dissipation | PD | 0.73 | W | TA = 25 °C, steady state | 1 | ||
| Power Dissipation | PD | 0.8 | W | TA = 70 °C, 5 s | 1 | ||
| Power Dissipation | PD | 0.47 | W | TA = 70 °C, steady state | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Maximum Junction-to-Ambient | RthJA | 80 | 100 | °C/W | t ≤ 5 s | 1 | |
| Maximum Junction-to-Ambient | RthJA | 130 | 170 | °C/W | Steady state | 1 | |
| Maximum Junction-to-Foot | RthJF | 45 | 55 | °C/W | Steady state | 1 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | pattern, a plane of copper overlies the drain pin and provides | 6 |
CAD (KiCad official)
- Symbol:
SI2328DS-T1-GE3 - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
si2328ds-t1-ge3-etched.step/si2328ds-t1-ge3-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si2328ds-t1-ge3.step/si2328ds-t1-ge3.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Vishay Intertech datasheet (8 pp, sha256
cb0114a6e6d57abd, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).