SN6505DQDBVRQ1 from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1	output	Open drain output of the first power MOSFETs, typically connected to the outer terminals of the center tap transformer, with external traces kept short because large currents flow through this pin.
2	VCC	power_in	Device supply pin that should be bypassed with a 4.7 μF or greater, low ESR capacitor, and an internal undervoltage lockout trips and turns both outputs off when VCC ≤ 2.25 V.
3	D2	output	Open drain output of the second power MOSFETs, typically connected to the outer terminals of the center tap transformer, with external traces kept short because large currents flow through this pin.
4	GND	power_in	Ground connected to the source of the power MOSFET switches via an internal sense circuit, which must be connected to a low-inductance quality ground plane because large currents flow through it.
5	EN	input	Enable pin that turns the device on or off, where grounding or leaving it floating disables all internal circuitry and it should be tied directly to VCC if unused.
6	CLK	input	Clock input used to run the device with an external clock, internally pulled down to GND, and the device automatically shifts to internal clock if no valid clock is detected on this pin.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOT-23-6
Category	Power Management (PMIC)
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		6	V		4
Voltage on EN, CLK	EN, CLK	-0.5			V	max VCC + 0.5 (footnote 3: must not exceed 6 V)	4
Output switch voltage	D1, D2			16	V		4
Peak output switch current	I(D1)Pk, I(D2)Pk			2.4	A		4
Junction temperature	TJ	-40		150	°C		4
Storage temperature range	Tstg	-65		150	°C		4
ESD human-body model	V(ESD)	-6000		6000	V	HBM, per AEC Q100-002	4
ESD charged-device model	V(ESD)	-1500		1500	V	CDM, per AEC Q100-011	4
Supply voltage	VCC	2.25		5.5	V		4
Output switch current, primary side	ID1, ID2			0.75	A	2.25 V ≤ VCC ≤ 2.8 V	4
Output switch current, primary side	ID1, ID2			1	A	2.8 V < VCC ≤ 5.5 V	4
Ambient temperature	TA	-40		125	°C		4
Supply current (SN6505B-Q1 and SN6505D-Q1)	I(Vcc)		1.56	2.3	mA	2.8 V ≤ VCC ≤ 5.5 V; RL = 50 Ω	5
Leakage current on EN and CLK pin	IIH		10	20	µA	EN / CLK = VCC	5
D1, D2 average switching frequency (SN6505B-Q1 and SN6505D-Q1)	FSW	363	424	517	kHz	RL = 50 Ω to VCC; Refer to Figure 7-3.	5
External clock frequency on CLK pin (SN6505B-Q1 and SN6505D-Q1)	F(EXT)	100		1600	kHz		5
Output switch on resistance	R(ON)		0.16	0.25	Ω	VCC = 4.5 V, ID1, ID2 = 1 A	5
Output switch on resistance	R(ON)		0.19	0.31	Ω	VCC = 2.8 V, ID1, ID2 = 1 A	5
Output switch on resistance	R(ON)		0.21	0.45	Ω	VCC = 2.25 V, ID1, ID2 = 0.5 A	5
Current clamp limit	ILIM	1.42	1.75	2.15	A	2.8 V < VCC ≤ 5.5 V	5
Current clamp limit	ILIM	0.65		1.85	A	2.25 V ≤ VCC ≤ 2.8 V	5
TSD turn on temperature	TSD+	154	168	181	°C		5
TSD turn off temperature	TSD-	135	150	166	°C		5
TSD hysteresis	TSD-	13		17	°C		5
Duration after which device switches to internal clock in case of invalid external clock	tCLKTIMER	10		25	µs		6
Power up time (2.25 V ≤ VCC < 3 V)	tPWRUP	75		160	µs	From EN=1 to full drive-current available at D1 and D2; 2.25 V ≤ VCC < 3 V	6
Power up time (3 V ≤ VCC ≤ 5.5 V)	tPWRUP	60		100	µs	From EN=1 to full drive-current available at D1 and D2; 3 V ≤ VCC ≤ 5.5 V	6
Power down time	tPWRDN	1		5	µs	From EN=0 to output MOSFETs off (no current on D1 and D2)	6
Junction-to-ambient thermal resistance	RθJA		137.7		°C/W		4
Junction-to-case (top) thermal resistance	RθJC(top)		57.7		°C/W		4
Junction-to-board thermal resistance	RθJB		46		°C/W		4
Junction-to-top characterization parameter	ψJT		13.4		°C/W		4
Junction-to-board characterization parameter	ψJB		44.9		°C/W		4

CAD (KiCad official)

Symbol: SN6505DQDBVRQ1
Footprint: Package_TO_SOT_SMD:SOT-23-6
3D model: SOT-23-6 (KiCad packages3D, STEP)
3D model files: sn6505dqdbvrq1-etched.step / sn6505dqdbvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn6505dqdbvrq1.step / sn6505dqdbvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 3c8af11607815139, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN6505DQDBVRQ1

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3D Model

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Schematic Symbol

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