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GM1203BACPZ-3-R7
Public Made by Adomby adom
GONGMOSEMI Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownGM1203BACPZ-3-R7
GONGMOSEMI · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(3.5x3.5)
GM1203BACPZ-3-R7 from GONGMOSEMI, in a QFN-20(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output; a ceramic capacitor of at least 47 µF is required from this pin to GND, placed as close to the pin as possible. |
| 2 | SNS | input | Output sense pin, connected internally to the output through an R0 resistor; connect it to the load side of the output only when the VOUT programming pins are used, otherwise leave it floating. |
| 3 | FB | input | Feedback pin to the error amplifier; a 10 nF feed-forward capacitor from FB to OUT, placed close to the device, is recommended, and FB to GND is rated −0.3 V to +3.6 V. |
| 4 | PG | output | Open-drain power-good output (active high) that indicates when the output reaches the PG rising threshold; use an external pull-up of 10 kΩ to 100 kΩ, and PG to GND is rated −0.3 V to +7 V with a PG current limit of −5 mA. |
| 5 | 50mV | input | Output-voltage programming pin for the 50 mV step; connect to GND or SNS or leave floating, where grounding it adds 50 mV to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 6 | 100mV | input | Output-voltage programming pin for the 100 mV step; connect to GND or SNS or leave floating, where grounding it adds 100 mV to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 7 | 200mV | input | Output-voltage programming pin for the 200 mV step; connect to GND or SNS or leave floating, where grounding it adds 200 mV to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 8 | GND | power_in | Ground pin that must be connected to the other GND pins and the exposed pad through a low-impedance path. |
| 9 | 400mV | input | Output-voltage programming pin for the 400 mV step; connect to GND or SNS or leave floating, where grounding it adds 400 mV to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 10 | 800mV | input | Output-voltage programming pin for the 800 mV step; connect to GND or SNS or leave floating, where grounding it adds 800 mV to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 11 | 1.6V | input | Output-voltage programming pin for the 1.6 V step; connect to GND or SNS or leave floating, where grounding it adds 1.6 V to the output voltage, and it is rated −0.3 V to VOUT+0.3 V. |
| 12 | BIAS | power_in | Bias supply pin that improves DC and AC performance and reduces power dissipation at VIN ≤ 2.2 V; it requires a 10 µF or larger capacitor to GND, and it must be left floating or grounded if unused. |
| 13 | NR/SS | passive | Noise-reduction and soft-start pin with an external capacitor to GND; a 10 nF or larger capacitor is recommended, and the pin is rated −0.3 V to +3.6 V. |
| 14 | EN | input | Enable pin: drive above 1.1 V to enable the device and below 0.4 V to disable it, and connect it to IN or BIAS if enable control is not used. |
| 15 | IN | power_in | Input pin that requires a ceramic capacitor of 10 µF or larger to GND placed close to the input, with an input voltage range of 1.1 V to 6.5 V. |
| 16 | IN | power_in | Input pin that requires a ceramic capacitor of 10 µF or larger to GND placed close to the input, with an input voltage range of 1.1 V to 6.5 V. |
| 17 | IN | power_in | Input pin that requires a ceramic capacitor of 10 µF or larger to GND placed close to the input, with an input voltage range of 1.1 V to 6.5 V. |
| 18 | GND | power_in | Ground pin that must be connected to the other GND pins and the exposed pad through a low-impedance path. |
| 19 | OUT | power_out | Regulated output; a ceramic capacitor of at least 47 µF is required from OUT to GND, placed as close to the pin as possible. |
| 20 | OUT | power_out | Regulated output; a ceramic capacitor of at least 47 µF is required from OUT to GND, placed as close to the pin as possible. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GONGMOSEMI |
| Package | QFN-20(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN, BIAS, PG, EN 至 GND 电压 | -0.3 | 7 | V | 8 | |||
| NR/SS, FB 至 GND 电压 | -0.3 | 3.6 | V | 8 | |||
| SNS, OUT 至 GND 电压 | -0.3 | V | 8 | ||||
| 50mV, 100mV, 200mV, 400mV, 800mV 至 GND 电压 | -0.3 | V | 8 | ||||
| PG 电流 | -5 | mA | 8 | ||||
| 存储温度范围 | -65 | 150 | °C | 8 | |||
| 工作温度范围 (-40°C 级，适用于本型号) | -40 | 125 | °C | 8 | |||
| 输入电压范围 (设计工作范围) | VIN | 1.1 | 6.5 | V | 18 | ||
| BIAS 偏置电压 (输入低于 1.5 V 时) | VBIAS | 3 | V | VIN < 1.5 V | 18 | ||
| 输入电容 (IN 到 GND) | CIN | 10 | µF | 6 | |||
| BIAS 到 GND 电容 | 10 | µF | 6 | ||||
| 输出电容 (OUT 到 GND, 陶瓷) | COUT | 47 | µF | 6 | |||
| 结到环境热阻 θJA (20 引脚 3.5 mm × 3.5 mm QFN) | θJA | 43.4 | °C/W | JEDEC 51-7 高有效导热四层测试板, 最坏情况 | 8 | ||
| VUVLO 带 BIAS 的最小 IN 电压 | VUVLO | 0.98 | 1.085 | V | VBIAS = 3.0 V 时，TJ = −40°C to +125°C | 9 | |
| VUVLO1 不带 BIAS 的最小 IN 电压 | VUVLO1 | 1.32 | 1.49 | V | TJ = −40°C to +125°C，VIN 逐渐上升 | 9 | |
| 最小 BIAS 输入电压 | VBIAS_UVLO | 2.2 | 2.9 | V | VIN = 1.1 V 时 VBIAS逐渐上升 | 9 | |
| VFB 输出电压 GM1203B 范围 (使用引脚编程) | VFB | 0.8 | 3.95 | V | 使用引脚编程 | 9 | |
| VFB 输出电压 GM1203B 范围 (使用外部电阻) | VFB | 0.8 | 5.5 | V | 使用外部电阻 | 9 | |
| 精度 | -1 | 1 | % | 0.5 V ≤ VOUT ≤ 3.65 V, 5 mA ≤ IOUT ≤ 3 A, over VIN | 9 | ||
| 带 BIAS 的精度 | -1 | 1.3 | % | VIN = 1.1 V, VOUT = 0.5V, 5 mA ≤ IOUT ≤ 3 A, 3.0 V ≤ VBIAS ≤ 6.5 V | 9 | ||
| ILIM 输出电流限制 | ILIM | 4.6 | 5.2 | 7.6 | A | VOUT 外加 0.9 × VOUT(nom), VIN = VOUT(nom) + 0.4 V | 9 |
| EN 引脚低电平输入电压 | VEN_IL | 0 | 0.4 | V | 9 | ||
| EN 引脚高电平输入电压 | VEN_IH | 1.1 | 6.5 | V | 9 | ||
| EN 引脚电流 | IEN | -0.1 | 0.1 | µA | VIN = 6.5 V, VEN = 0 V and 6.5 V | 9 | |
| PG 引脚阈值 下降 | VPG_FALLING | 82 | 91 | 93 | % × VOUT | 下降 | 9 |
| NR/SS 引脚充电电流 | INR/SS | 4 | 9 | 11.5 | µA | VNR/SS = GND, VIN = 6.5 V | 10 |
| FB 引脚漏电流 | IFB | -100 | 100 | nA | VIN = 6.5 V | 10 |
CAD (KiCad official)
- Symbol:
GM1203BACPZ-3-R7 - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: QFN-20(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gm1203bacpz-3-r7-etched.step/gm1203bacpz-3-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gm1203bacpz-3-r7.step/gm1203bacpz-3-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GONGMOSEMI datasheet (25 pp, sha256
f744d3090b584d94, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).