CY14B101NA-ZS45XIT from Cypress Semicon, in a TSOP-44. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	A0	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
2	A1	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
3	A2	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
4	A3	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
5	A4	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
6	CE	input	Chip Enable, active LOW; LOW selects the chip, HIGH deselects it.
7	DQ0	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
8	DQ1	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
9	DQ2	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
10	DQ3	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
11	VCC	power_in	Power supply input, 3.0 V +20%/-10% (2.7 V to 3.6 V).
12	VSS	power_in	Ground for the device; must be connected to system ground.
13	DQ4	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
14	DQ5	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
15	DQ6	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
16	DQ7	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
17	WE	input	Write Enable, active LOW; when chip is enabled and WE is LOW, data on the I/O pins is written to the addressed location.
18	A5	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
19	A6	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
20	A7	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
21	A8	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
22	A9	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
23	A10	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
24	A11	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
25	A12	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
26	A13	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
27	A14	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
28	VCAP	passive	AutoStore capacitor connection; supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements (61 µF min to 180 µF max to VSS).
29	DQ8	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
30	DQ9	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
31	DQ10	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
32	DQ11	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
33	VCC	power_in	Power supply input, 3.0 V +20%/-10% (2.7 V to 3.6 V).
34	VSS	power_in	Ground for the device; must be connected to system ground.
35	DQ12	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
36	DQ13	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
37	DQ14	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
38	DQ15	bidirectional	Bidirectional data I/O line, used as input or output depending on operation.
39	BLE	input	Byte Low Enable, active LOW; controls DQ7-DQ0.
40	BHE	input	Byte High Enable, active LOW; controls DQ15-DQ8.
41	OE	input	Output Enable, active LOW; enables the data output buffers during read cycles, I/O pins are tristated when OE is HIGH.
42	A15	input	Address input; A0-A15 select one of the 65,536 words in x16 configuration.
43	NC	unconnected	No connect; address expansion for 4-Mbit, pin not connected to the die.
44	NC	unconnected	No connect; address expansion for 2-Mbit, pin not connected to the die.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	TSOP-44
Category	Memory
Pins	44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply voltage	VCC	2.7	3	3.6	V	Over the Operating Range	10
Ambient temperature (Industrial)		-40		85	°C	Operating Range, Industrial	10
Average VCC current	ICC1			52	mA	tRC = 45 ns, values obtained without output loads (IOUT = 0 mA)	10
Average VCC current during STORE	ICC2			10	mA	All inputs don't care, VCC = Max, average current for duration tSTORE	10
Average VCC current at tRC = 200 ns	ICC3		35		mA	VCC(Typ), 25 °C, all inputs cycling at CMOS levels, IOUT = 0 mA	10
Average VCAP current during AutoStore cycle	ICC4			5	mA	All inputs don't care. Average current for duration tSTORE	10
VCC standby current	ISB			5	mA	CE > (VCC, 0.2 V), VIN < 0.2 V or > (VCC, 0.2 V), inputs static, f = 0 MHz	10
Input leakage current (except HSB)	IIX	-1		1	µA	VCC = Max, VSS < VIN < VCC	10
Input leakage current (for HSB)	IIX	-100		1	µA	VCC = Max, VSS < VIN < VCC	10
Off-state output leakage current	IOZ	-1		1	µA	VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL	10
Input HIGH voltage	VIH	2			V	Max VCC + 0.5 V	10
Input LOW voltage	VIL			0.8	V	Min VSS, 0.5 V	10
Output HIGH voltage	VOH	2.4			V	IOUT = -2 mA	10
Output LOW voltage	VOL			0.4	V	IOUT = 4 mA	10
Storage capacitor	VCAP	61	68	180	µF	Between VCAP pin and VSS	11
Data retention	DATAR	20			Years	Over the Operating Range	11
Nonvolatile STORE operations	NVC	1000			K	Over the Operating Range	11
Input capacitance (except BHE, BLE and HSB)	CIN			7	pF	TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)	11
Input capacitance (for BHE, BLE and HSB)	CIN			8	pF	TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)	11
Output capacitance (except HSB)	COUT			7	pF	TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)	11
Output capacitance (for HSB)	COUT			8	pF	TA = 25 °C, f = 1 MHz, VCC = VCC(Typ)	11
Thermal resistance junction to ambient	ΘJA		41.74		°C/W	44-pin TSOP II, EIA/JESD51	11
Thermal resistance junction to case	ΘJC		11.9		°C/W	44-pin TSOP II, EIA/JESD51	11
Storage temperature		-65		150	°C		10
Maximum junction temperature				150	°C		10
Supply voltage on VCC relative to VSS	VCC	-0.5		4.1	V		10
Voltage applied to outputs in High Z state		-0.5			V	Max VCC + 0.5 V	10
Input voltage		-0.5			V	Max VCC + 0.5 V	10
Transient voltage (< 20 ns) on any pin to ground		-2			V	Max VCC + 2.0 V	10
Package power dissipation capability				1	W	TA = 25 °C	10
DC output current				15	mA	1 output at a time, 1s duration	10
Surface mount Pb soldering temperature				260	°C	3 seconds	10
Static discharge voltage		2001			V	per MIL-STD-883, Method 3015 (printed > 2001 V)	10
Latch up current		200			mA	printed > 200 mA	10
Chip enable access time	tACE			45	ns	45 ns	13
Read cycle time	tRC	45			ns	45 ns	13
Address access time	tAA			45	ns	45 ns	13
Output enable to data valid	tDOE			20	ns	45 ns	13
Output hold after address change	tOHA	3			ns	45 ns	13
Chip enable to output active	tLZCE	3			ns	45 ns	13
Chip disable to output inactive	tHZCE			15	ns	45 ns	13
Output enable to output active	tLZOE	0			ns	45 ns	13
Output disable to output inactive	tHZOE			15	ns	45 ns	13
Chip disable to power standby	tPD			45	ns	45 ns	13
Byte enable to data valid	tDBE			20	ns	45 ns	13
Write cycle time	tWC	45			ns	45 ns	13
Write pulse width	tPWE	30			ns	45 ns	13
Chip enable to end of write	tSCE	30			ns	45 ns	13
Data setup to end of write	tSD	15			ns	45 ns	13
Address setup to end of write	tAW	30			ns	45 ns	13
Write enable to output disable	tHZWE			15	ns	45 ns	13
Output active after end of write	tLZWE	3			ns	45 ns	13
Byte enable to end of write	tBW	30			ns	45 ns	13
Power-Up RECALL duration	tHRECALL			20	ms	45 ns	16
STORE cycle duration	tSTORE			8	ms	45 ns	16
Low voltage trigger level	VSWITCH			2.65	V	45 ns column	16

CAD (KiCad official)

Symbol: CY14B101NA-ZS45XIT
Footprint: Package_SO:TSOP-II-44_10.16x18.41mm_P0.8mm
3D model: TSOP-44 (KiCad packages3D, STEP)
3D model files: cy14b101na-zs45xit-etched.step / cy14b101na-zs45xit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy14b101na-zs45xit.step / cy14b101na-zs45xit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (31 pp, sha256 38d6da3b80b200ff, retrieved 2026-10-30, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY14B101NA-ZS45XIT

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Schematic Symbol

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