MAX9744ETH+T from MAX, in a TQFN-44(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	BOOTL+	passive	Left-channel positive speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOTL+ and OUTL+.
2	OUTL+	output	Left-channel speaker output, positive phase.
3	OUTL+	output	Left-channel speaker output, positive phase.
4	PVDD	power_in	Speaker amplifier power-supply input, 4.5V to 14V; bypass each with a 1µF capacitor to PGND.
5	PVDD	power_in	Speaker amplifier power-supply input, 4.5V to 14V; bypass each with a 1µF capacitor to PGND.
6	VDD	power_in	Power-supply input for the remainder of the device, 2.7V to 3.6V; bypass each with a 1µF capacitor to GND.
7	GND	power_in	Ground.
8	SDA/VOL	bidirectional	I2C serial data I/O and analog volume control input.
9	SCLK/PWM	input	In I2C mode acts as serial clock input; when ADDR1 and ADDR2 = GND, SCLK = 1 selects standard PWM and SCLK = 0 selects filterless modulation.
10	VDD	power_in	Power-supply input for the remainder of the device, 2.7V to 3.6V; bypass each with a 1µF capacitor to GND.
11	GND	power_in	Ground.
12	GND	power_in	Ground.
13	ADDR1	input	Address select input 1 sets the I2C device address; connect ADDR1 and ADDR2 to GND to select analog volume control mode.
14	ADDR2	input	Address select input 2 sets the I2C device address; connect ADDR1 and ADDR2 to GND to select analog volume control mode.
15	GND	power_in	Ground.
16	INL	input	Left-channel audio input.
17	FBL	output	Left-channel feedback; connect feedback resistor between FBL and INL to set amplifier gain.
18	FBR	output	Right-channel feedback; connect feedback resistor between FBR and INR to set amplifier gain.
19	INR	input	Right-channel audio input.
20	BIAS	passive	Common-mode bias voltage (1.5V typical); bypass with a 2.2µF capacitor to GND.
21	VDD	power_in	Power-supply input for the remainder of the device, 2.7V to 3.6V; bypass each with a 1µF capacitor to GND.
22	SHDN	input	Shutdown input; drive low to disable the audio amplifiers, and connect to VDD or drive high for normal operation.
23	N.C.	unconnected	No connection; not internally connected.
24	MUTE	input	Mute input; drive high to mute the speaker outputs, and connect to GND for normal operation.
25	SYNC	input	Frequency select and external clock input: GND selects 1200kHz fixed-frequency, unconnected selects 1440kHz, VDD selects spread-spectrum 1200kHz ±30kHz, and a clock of 1000kHz to 1600kHz synchronizes the device with fSW = 1/4 fSYNC.
26	SYNCOUT	output	SYNC signal output for cascading devices.
27	GND	power_in	Ground.
28	VDD	power_in	Power-supply input for the remainder of the device, 2.7V to 3.6V; bypass each with a 1µF capacitor to GND.
29	PVDD	power_in	Speaker amplifier power-supply input, 4.5V to 14V; bypass each with a 1µF capacitor to PGND.
30	PVDD	power_in	Speaker amplifier power-supply input, 4.5V to 14V; bypass each with a 1µF capacitor to PGND.
31	OUTR+	output	Right-channel positive speaker output.
32	OUTR+	output	Right-channel positive speaker output.
33	BOOTR+	passive	Right-channel positive speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOTR+ and OUTR+.
34	PGND	power_in	Power ground.
35	PGND	power_in	Power ground.
36	OUTR-	output	Right-channel negative speaker output.
37	OUTR-	output	Right-channel negative speaker output.
38	BOOTR-	passive	Right-channel negative speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOTR- and OUTR-.
39	PGND	power_in	Power ground.
40	BOOTL-	passive	Left-channel negative speaker output boost flying-capacitor connection; connect a 0.1µF ceramic capacitor between BOOTL- and OUTL-.
41	OUTL-	output	Left-channel negative speaker output.
42	OUTL-	output	Left-channel negative speaker output.
43	PGND	power_in	Power ground.
44	PGND	power_in	Power ground.
45	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	MAX
Package	TQFN-44(7x7)
Category	Amplifiers
Pins	45

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Speaker Amplifier Supply Voltage Range	PVDD	4.5		14	V	Inferred from PSRR test	2
Supply Voltage Range	VDD	2.7		3.6	V	Inferred from PSRR test	2
Input Amplifier Output Short-Circuit Current Limit		-60		60	mA		2
Output Offset	VOS	-15	2	15	mV	TA = 25°C	2
Hard Output Current Limit	ISC	3.9		5.5	A		3
Quiescent Current (IDD)	IDD		20	35	mA		2
Quiescent Current (IPVDD)	IPVDD		10	20	mA		2
Shutdown Current (IVDD)	IVDDSHDN		0.1	1	µA	TA = +25°C	2
Shutdown Current (IPVDD)	IPVDDSHDN		0.1	1	µA	TA = +25°C	2
Digital Input Leakage Current	ILK	-1		1	µA	TA = +25°C	4
VOL Input Leakage Current		-5		5	µA		4
SYNC Input Leakage Current	ISYNCIN	-13	7.5	13	µA	TA = +25°C	5
Class D Switching Frequency (fSW), SYNC = GND	fSW	255	300	338	kHz	SYNC = GND	4
Class D Switching Frequency (fSW), SYNC unconnected	fSW	320	360	410	kHz	SYNC = unconnected	4
Class D Switching Frequency (fSW) spread, spread-spectrum	fSW	-6	300	6	kHz	SYNC = VDD (spread-spectrum mode); printed as 300 ±6 kHz	4
SYNC Frequency (fSYNC), SYNC = GND	fSYNC	1020	1200	1355	kHz	SYNC = GND	4
SYNC Frequency (fSYNC), SYNC unconnected	fSYNC	1280	1440	1640	kHz	SYNC = unconnected	4
SYNC Frequency (fSYNC) spread, spread-spectrum	fSYNC	-30	1200	30	kHz	SYNC = VDD (spread-spectrum mode); printed as 1200 ±30 kHz	4
SYNC Frequency Lock Range		1000		1600	kHz		4
Minimum SYNC Frequency Lock Duty Cycle		40			%		4
Maximum SYNC Frequency Lock Duty Cycle				60	%		4
I2C Data Hold Time	tHD,DAT	0		0.9	µs		5
Pulse Width of Spike Suppressed	tSP	0		50	ns		5
Rise Time of SDA and SCL, Receiving	tR			300	ns	Receiving; Note 6; minimum printed as 20 + 0.1CB (expression, not numeric)	5
Fall Time of SDA and SCL, Receiving	tF			300	ns	Receiving; Note 6; minimum printed as 20 + 0.1CB (expression, not numeric)	5
Speaker Amplifier Supply Voltage (absolute maximum)	PVDD			16	V	PVDD to PGND	2
VDD to GND (absolute maximum)	VDD			4	V	VDD to GND	2
Logic pins to GND (FB_, SYNCOUT, SYNC, SDA/VOL, ADDR1, ADDR2)		-0.3			V	Maximum printed as VDD + 0.3V (expression, not numeric)	2
BOOT_ to VDD		-0.3		6	V	BOOT_ to VDD	2
BOOT_ to OUT_		-0.3		6	V	BOOT_ to OUT_	2
OUT_ to GND		-0.3			V	Maximum printed as PVDD + 0.3V (expression, not numeric)	2
PGND to GND		-0.3		0.3	V	PGND to GND	2
Any other pin to GND		-0.3		4	V	Any other pin to GND	2
Continuous Input Current (except OUT_)		-20		20	mA	Continuous	2
Junction Temperature				150	°C		2
Storage Temperature Range		-65		150	°C		2
Lead Temperature				300	°C	Soldering, 10s	2
Operating Temperature Range		-40		85	°C		2
Thermal Resistance, junction-to-ambient, single-layer board	θJA			37	°C/W	Single-layer board	2
Thermal Resistance, junction-to-ambient, multilayer board	θJA			27	°C/W	Multilayer board	2

CAD (KiCad official)

Symbol: MAX9744ETH+T
Footprint: Package_DFN_QFN:QFN-44-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: TQFN-44(7x7) (KiCad packages3D, STEP)
3D model files: max9744eth-t-etched.step / max9744eth-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); max9744eth-t.step / max9744eth-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: MAX datasheet (28 pp, sha256 0af23e8c2d55295d, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

MAX9744ETH+T

Verified MAX9744ETH+T

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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